# US 2014/0151876 A1 · Semiconductor package and process for fabricating same

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- Number: US 2014/0151876 A1
- Document ID: US20140151876A1
- Status: Published application
- Kind: A1
- Application number: 14/174,364
- Filed: 2014-02-06
- Published: 2014-06-05
- Earliest claimed: 2009-10-14
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Yuan-Chang Su; Shih-Fu Huang; Chia-Cheng Chen; Chia-Hsiung Hsieh; Tzu-Hui Chen; Kuang-Hsiung Chen; Pao-Ming Hsieh
- Web page: https://patentgrep.com/patent/US20140151876A1

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/635: {Through-vias}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 72/01308: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/07311: {Treating the bonding area before connecting, e.g. by applying flux or cleaning}
- H10W 72/30: Die-attach connectors
- H10W 72/50: Bond wires
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/737: {between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A semiconductor package, comprising:
a substrate, including:
a dielectric layer having a plurality of openings;
a conductive layer disposed adjacent to the dielectric layer;
a plurality of conductive vias disposed in respective ones of the openings; and
an etching stop layer disposed in the openings and contacting a top end of each of the plurality of conductive vias;
wherein the conductive layer and the conductive vias are formed of the same material;
a chip attached to a top side of the substrate and connected to the conductive layer; and
a plurality of conductive bumps disposed adjacent to respective ones of the conductive vias,
wherein the etching stop layer is connected to the conductive layer at a bottom surface of the conductive layer, and a bottom end of each conductive via is connected to the respective conductive bump such that the bottom end of the conductive via does not protrude from the respective opening.

### Claim 22 (depends on 21)

The semiconductor package of claim 21, wherein the openings extend from a bottom surface of the dielectric layer to the conductive layer.

### Claim 23 (depends on 21)

The semiconductor package of claim 21, wherein an end of each conductive via has a curved profile.

### Claim 24 (depends on 21)

The semiconductor package of claim 21, further comprising: a solder resist layer, disposed adjacent to a top surface of the conductive layer and exposing portions of the conductive layer.

### Claim 25 (depends on 24)

The semiconductor package of claim 24, further comprising: an adhesive layer, disposed between the chip and the solder resist layer.

### Claim 26 (depends on 24)

The semiconductor package of claim 24, wherein the solder resist layer has an opening disposed adjacent to the chip and exposing a portion of the conductive layer, and further comprising: an adhesive layer, disposed in the opening of the solder resist layer and disposed between the chip and the exposed portion of the conductive layer.

### Claim 27 (depends on 21)

The semiconductor package of claim 21, wherein a height of each conductive via is substantially equal to a depth of the respective opening.

### Claim 28 (depends on 21)

The semiconductor package of claim 21, wherein the bottom end of each conductive via is recessed from a bottom surface of the dielectric layer.

### Claim 29 (depends on 21)

The semiconductor package of claim 21, wherein the conductive vias are configured to relieve mechanical stress to the package.

### Claim 30 (depends on 21)

The semiconductor package of claim 21, wherein the conductive layer covers a top end of each opening.

### Claim 31 (depends on 21)

The semiconductor package of claim 21, wherein the bottom end of each conductive via is concave.

### Claim 32

A substrate, comprising:
a dielectric layer having a plurality of openings with sidewalls extending between a first surface of the dielectric layer and a second surface of the dielectric layer;
a conductive material disposed within the plurality of openings;
a barrier layer disposed over the conductive material;
a patterned conductive layer in physical contact with the dielectric layer, and in electrical contact with the conductive material through the barrier layer, wherein the patterned conductive layer is formed of the same material as the conductive material; and
a solder resist layer disposed on the patterned conductive layer and exposing portions of the patterned conductive layer to form a plurality of contact pads.

### Claim 33 (depends on 32)

The substrate of claim 32, wherein a surface of the conductive material is recessed from the second surface of the dielectric layer.

### Claim 34 (depends on 33)

The substrate of claim 33, further comprising a plurality of solder balls disposed within the plurality of openings and in electrical contact with the conductive material, the plurality of solder balls extending beyond the second surface of the dielectric layer and covering a portion of the second surface of the dielectric layer outside of the plurality of openings.

### Claim 35 (depends on 32)

The substrate of claim 32, wherein at least a portion of a surface of the conductive material is aligned with the second surface of the dielectric layer.

### Claim 36 (depends on 35)

The substrate of claim 35, further comprising a plurality of solder balls disposed in electrical contact with the conductive material, the plurality of solder balls covering a portion of the second surface of the dielectric layer outside of the plurality of openings.

### Claim 37 (depends on 32)

The substrate of claim 32, further comprising an adhesive layer disposed over at least one of the plurality of contact pads.

### Claim 38 (depends on 32)

The substrate of claim 32, wherein a height of the conductive material is substantially equal to a depth of the plurality of openings.

### Claim 39 (depends on 32)

The substrate of claim 32, wherein the conductive layer covers an end of each opening.

### Claim 40 (depends on 32)

The substrate of claim 32, wherein the conductive material is copper.