# US 2014/0151875 A1 · Crosstalk polarity reversal and cancellation through substrate material tuning

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- Number: US 2014/0151875 A1
- Document ID: US20140151875A1
- Status: Published application
- Kind: A1
- Application number: 14/171,714
- Filed: 2014-02-03
- Published: 2014-06-05
- Earliest claimed: 2012-10-31
- Assignees: Intel Corporation
- Inventors: Zhichao ZHANG; Tolga Memioglu; Tao Wu; Kemal Aygun
- Web page: https://patentgrep.com/patent/US20140151875A1

## CPC

- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H01P 3/081: {Microstriplines}
- H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H05K 1/0216: {Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215)}
- H05K 1/0228: {Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245)}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

## Claims

### Claim 1

A system comprising:
a first integrated circuit (IC) chip having a first and second input/output (I/O) channels;
a substrate affixed to the IC chip through first interconnect bumps, the substrate including transmission line circuitry further comprising:
a first conductive trace defining a routing path for the first I/O channel on a first metallization level disposed over a package substrate;
a second conductive trace defining a routing path for the second I/O channel on the first metallization level;
a first dielectric material disposed between the first and second conductive traces;
a ground plane on a second metallization level disposed over the substrate and above or below the first metallization level; and
a second dielectric material disposed between the ground plane and the first and second conductive traces, wherein the second dielectric material has a different dielectric constant than that of the first dielectric material; and
second bumps coupling the first and second I/O channels to a second IC chip.

### Claim 2 (depends on 1)

The system of claim 1, wherein the first and second dielectric materials have dielectric constants sufficiently different to induce far end crosstalk (FEXT) between the first and second I/O channels that is of opposite polarity than that induced by the first and second bumps to a least partially cancel overall channel FEXT.

### Claim 3 (depends on 2)

The system of claim 2, wherein the first and second I/O channels are each coupled to a single-ended driver and wherein the difference in dielectric constants between the first and second dielectric materials increases mutual capacitance or decreases self-capacitance of the transmission line circuitry relative to reference amounts associated with the circuitry implemented with a single dielectric constant.

### Claim 4 (depends on 2)

The system of claim 2, wherein the first and second I/O channels are each coupled to differential driver and wherein the difference in dielectric constants between the first and second dielectric materials reduces mutual capacitance or increases self-capacitance of the transmission line circuitry relative to reference amounts associated with the circuitry implemented with a single dielectric constant.

### Claim 5 (depends on 1)

The system of claim 1, wherein the first IC is a microprocessor and the second IC is a synchronous dynamic random-access memory (SDRAM).

### Claim 6

A method of fabricating transmission line circuitry for coupling a first and second input/output (I/O) channel of an integrated circuit (IC) disposed on a chip to an off-chip connection point, the method comprising:
forming a first conductive trace defining a routing path for the first I/O channel in a first metallization level disposed over a substrate;
forming a second conductive trace defining a routing path for the second I/O channel in the first metallization level;
forming a first dielectric material disposed between the first and second conductive traces;
forming a ground plane in a second metallization level disposed over the substrate and above or below the first metallization level; and
forming a second dielectric material disposed between the ground plane and the first and second conductive traces, wherein the second dielectric material has a different dielectric constant than that of the first dielectric material.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the first and second dielectric materials further comprises laminating a multi-layered film over the first and second conductive traces.

### Claim 8 (depends on 6)

The method of claim 6, wherein forming the second dielectric layer comprises laminating the second dielectric layer onto the first dielectric layer, and wherein forming the first and second conductive traces further comprises:
forming openings of different lateral dimensions in the first and second dielectric layers; and
depositing metallization into the openings.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second dielectric layer is laminated onto the first dielectric layer after openings are formed in the first dielectric layers.