# US 2014/0151874 A1 · Bump-equipped electronic component and method for manufacturing bump-equipped electronic component > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151874 A1 - Document ID: US20140151874A1 - Status: Published application - Kind: A1 - Application number: 14/096,044 - Filed: 2013-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Isao OBU; Shinya OSAKABE - Web page: https://patentgrep.com/patent/US20140151874A1 ## CPC - H03H 9/0514: {consisting of mounting pads or bumps} - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 3/195: in integrated circuits - H03F 3/213: in integrated circuits - H03H 9/059: {consisting of mounting pads or bumps} - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/318: A matching circuit being used as coupling element between two amplifying stages - H03F 2200/451: the amplifier being a radio frequency amplifier - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H03F: AMPLIFIERS ## Abstract A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface. ## Claims ### Claim 1 A bump-equipped electronic component comprising: a circuit substrate; and first and second bumps disposed on a principal surface of the circuit substrate and having different cross-sectional areas in a direction parallel or substantially parallel to the principal surface; wherein one of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface. ### Claim 2 (depends on 1) The bump-equipped electronic component according to claim 1, wherein the height adjustment layer is disposed on a top end of the bump provided with the height adjustment layer. ### Claim 3 (depends on 1) The bump-equipped electronic component according to claim 1, wherein the height adjustment layer is disposed in a central portion in the perpendicular or substantially perpendicular direction of the bump provided with the height adjustment layer. ### Claim 4 (depends on 1) The bump-equipped electronic component according to claim 1, wherein the height adjustment layer and the bump provided with the height adjustment layer have the same cross-sectional area in the direction parallel or substantially parallel to the principal surface. ### Claim 5 (depends on 1) The bump-equipped electronic component according to claim 1, wherein the height adjustment layer has a resistivity that is different from a resistivity of a main material constituting the bump provided with the height adjustment layer. ### Claim 6 (depends on 1) The bump-equipped electronic component according to claim 1, wherein each of the first and second bumps includes a solder layer disposed at a top end thereof, and the solder layer of one of the first and second bumps having a larger cross-sectional area in the direction parallel or substantially parallel to the principal surface has a higher melting point than that of the solder layer of the bump having a smaller cross-sectional area in the direction parallel or substantially parallel to the principal surface. ### Claim 7 A bump-equipped electronic component comprising: a circuit substrate; and first and second bumps disposed on a principal surface of the circuit substrate and having different cross-sectional areas in a direction parallel or substantially parallel to the principal surface of the substrate; wherein each of the first and second bumps includes a height adjustment layer arranged to adjust a height from the principal surface of the substrate to a standard height. ### Claim 8 (depends on 7) The bump-equipped electronic component according to claim 7, wherein each of the height adjustment layers is disposed on a top end of the respective one of the first and second bumps. ### Claim 9 (depends on 7) The bump-equipped electronic component according to claim 7, wherein the height adjustment layer is disposed in a central portion in the perpendicular or substantially perpendicular direction of the respective one of the first and second bumps. ### Claim 10 (depends on 7) The bump-equipped electronic component according to claim 7, wherein each of the height adjustment layers and the corresponding one of the first and second bumps bump have the same cross-sectional area in the direction parallel or substantially parallel to the principal surface. ### Claim 11 (depends on 7) The bump-equipped electronic component according to claim 7, wherein each of the height adjustment layers has a resistivity that is different from a resistivity of a main material constituting the respective one of the first and second bumps. ### Claim 12 (depends on 7) The bump-equipped electronic component according to claim 7, wherein each of the first and second bumps includes a solder layer disposed at a top end thereof, and the solder layer of one of the first and second bumps having a larger cross-sectional area in the direction parallel or substantially parallel to the principal surface has a higher melting point than that of the solder layer of the bump having a smaller cross-sectional area in the direction parallel or substantially parallel to the principal surface. ### Claim 13 A method for manufacturing a bump-equipped electronic component, the method comprising: a step of forming first and second bumps on a principal surface of a circuit substrate, the first and second bumps having different cross-sectional areas in a direction parallel or substantially parallel to the principal surface; wherein the step of forming the bumps includes a step of forming a height adjustment layer in a direction perpendicular or substantially perpendicular to the principal surface when one of the first and second bumps having a smaller cross-sectional area is formed. ### Claim 14 (depends on 13) The method according to claim 13, wherein the step of forming the bumps includes a step of forming the height adjustment layer on each of the first and second bumps. ### Claim 15 (depends on 13) The method according to claim 13, wherein the height adjustment layer is disposed on a top end of the bump provided with the height adjustment layer. ### Claim 16 (depends on 13) The method according to claim 13, wherein the height adjustment layer is disposed in a central portion in the perpendicular or substantially perpendicular direction of the bump provided with the height adjustment layer. ### Claim 17 (depends on 13) The method according to claim 13, wherein the height adjustment layer and the bump provided with the height adjustment layer have the same cross-sectional area in the direction parallel or substantially parallel to the principal surface. ### Claim 18 (depends on 13) The method according to claim 13, wherein the height adjustment layer has a resistivity that is different from a resistivity of a main material constituting the bump provided with the height adjustment layer. ### Claim 19 (depends on 13) The method according to claim 13, wherein each of the first and second bumps includes a solder layer disposed at a top end thereof, and the solder layer of one of the first and second bumps having a larger cross-sectional area in the direction parallel or substantially parallel to the principal surface has a higher melting point than that of the solder layer of the bump having a smaller cross-sectional area in the direction parallel or substantially parallel to the principal surface.