# US 2014/0151866 A1 · Packaged Semiconductor Device with Tensile Stress and Method of Making a Packaged Semiconductor Device with Tensile Stress > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151866 A1 - Document ID: US20140151866A1 - Status: Published application - Kind: A1 - Application number: 13/691,587 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Ralf Otremba - Web page: https://patentgrep.com/patent/US20140151866A1 ## CPC - H10W 90/811: {Multiple chips on leadframes} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/40: Leadframes - H10W 70/417: {Bonding materials between chips and die pads} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 74/47: comprising organic materials, e.g. plastics or resins - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10W 72/075: {of bond wires} - H10W 72/07541: {Controlling the environment, e.g. atmosphere composition or temperature} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein the second thickness is larger than the first thickness. ## Claims ### Claim 1 An assembled device comprising: a carrier comprising a first thickness; a connection layer disposed on the carrier; and a chip disposed on the connection layer, the chip comprising a second thickness, wherein the second thickness is larger than the first thickness. ### Claim 2 (depends on 1) The assembled device according to claim 1, wherein the second thickness is equal to or greater than 50 μm and the first thickness is equal to or less than 50 μm. ### Claim 3 (depends on 1) The assembled device according to claim 1, wherein the second thickness is equal to or greater than 100 μm and the first thickness is equal to or less than 100 μm. ### Claim 4 (depends on 1) The assembled device according to claim 1, wherein the connection layer comprises a third thickness, the third thickness being between 1 μm and 3 μm. ### Claim 5 (depends on 4) The assembled device according to claim 4, wherein the connection layer is a diffusion solder layer. ### Claim 6 (depends on 1) The assembled device according to claim 1, wherein a top surface of the chip comprises a tensile stress and wherein a bottom surface of the chip comprises a compressive stress. ### Claim 7 (depends on 6) The assembled device according to claim 6, wherein the tensile stress is equal to or greater than 100 MPa. ### Claim 8 An assembled device comprising: a carrier; a connection layer disposed on the carrier; and a planar chip comprising a top surface and a bottom surface, the planar chip being disposed with the bottom surface on the connection layer, wherein the top surface of the planar chip comprises a tensile stress. ### Claim 9 (depends on 8) The assembled device according to claim 8, wherein the tensile stress is equal to or greater than 100 MPa. ### Claim 10 (depends on 9) The assembled device according to claim 9, further comprising a compressive stress at the bottom surface of the chip. ### Claim 11 (depends on 10) The assembled device according to claim 10, further comprising interconnects connecting chip contact pads with carrier contact pads; and an encapsulation encapsulating the carrier, the connection layer and the planar chip. ### Claim 12 (depends on 8) The assembled device according to claim 8, wherein the connection layer comprises a thickness of equal to or less than 20 μm. ### Claim 13 An assembled device comprising: a carrier; a connection layer disposed on the carrier; and a chip comprising a top surface and a bottom surface, the chip being disposed with the bottom surface on the connection layer, the chip further comprising a first source/drain contact at the top surface and a second source/drain contact at the top surface, wherein the chip comprises a tensile stress between the first source/drain contact and the second source drain contact. ### Claim 14 (depends on 13) The assembled device according to claim 13, wherein the tensile stress is equal to or greater than 100 MPa. ### Claim 15 (depends on 13) The assembled device according to claim 13, wherein the chip comprises a power semiconductor device. ### Claim 16 (depends on 15) The assembled device according to claim 15, wherein the connection layer comprises an organic adhesive layer or an inorganic adhesive layer with a thickness of equal to or less than 20 μm. ### Claim 17 (depends on 15) The assembled device according to claim 15, wherein the connection layer comprises a diffusion soldered layer with a thickness of equal to or less than 3 μm. ### Claim 18 A method of manufacturing a semiconductor device, the method comprising: placing a semiconductor substrate with a bottom main surface onto a leadframe thereby forming a tensile stress at a top main surface of the semiconductor substrate, the leadframe comprising a larger thickness than the semiconductor substrate. ### Claim 19 (depends on 18) The method according to claim 18, further comprising thinning the semiconductor substrate before placing the semiconductor substrate on the leadframe. ### Claim 20 (depends on 18) The method according to claim 18, wherein placing the semiconductor substrate onto leadframe comprises diffusion soldering the semiconductor substrate onto the leadframe.