# US 2014/0151865 A1 · Semiconductor device packages providing enhanced exposed toe fillets > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151865 A1 - Document ID: US20140151865A1 - Status: Published application - Kind: A1 - Application number: 13/689,845 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Inventors: Thomas H. Koschmieder - Web page: https://patentgrep.com/patent/US20140151865A1 ## CPC - H10W 74/016: {using moulds} - H10W 70/427: {Bent parts} - H10W 70/429: {being the outer leads} - H10W 70/457: {of metallic layers on leadframes} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A mechanism is provided by optically inspectable surface mount bonding of no-leads packages is enhanced. Embodiments of the present invention use a lead frame within the no-leads package that provides a plated surface not only along the bottom of the package but also in a direction substantially parallel to the sides of the package. Since the plated surface has a greater affinity for solder during a reflow process than does the bare metal of the lead frame, toe fillets have a greater chance of forming in a manner that can be optically inspected during a test for quality of the bonding of the package to a printed circuit board. In addition, a mold chase that conforms to the shape of the lead frame is used to prevent mold compound from adhering to the portions of the lead frame external to the package that are used as electrical contacts. ## Claims ### Claim 1 A semiconductor device package comprising: a body formed from an encapsulant, wherein the body comprises first and second major surfaces, the body comprises at least one side surface coupling the first and second major surfaces, and the first and second major surfaces are substantially parallel and at least a first portion of the side surface is substantially perpendicular to the first major surface and joins the first major surface at an edge of the body; an electrical contact having a first exposed surface on the first major surface of the semiconductor device package body and a second exposed surface substantially parallel to the first portion of the at least one side surface, wherein the first exposed surface and the second exposed surface of the electrical contact are connected at a first bend in the electrical contact, the first exposed surface and the second exposed surface of the electrical contact are comprised of a solderable metal, and the second exposed surface of the electrical contact is recessed from the first portion of the at least one side surface. ### Claim 2 (depends on 1) The semiconductor device package of claim 1 wherein the electrical contact comprises: a first metal layer comprising copper; and a second metal layer coating the first metal layer and comprising a solderable surface, wherein the first exposed surface and the second exposed surface of the electrical contact comprise the solderable surface. ### Claim 3 (depends on 2) The semiconductor device package of claim 2 wherein the second metal layer comprises one or more of tin, lead, gold, silver, nickel, and palladium. ### Claim 4 (depends on 2) The semiconductor device package of claim 2 further comprising: a portion of a lead frame encapsulated in the body of the semiconductor device package, wherein the portion of the lead frame comprises the electrical contact and a die pad; a semiconductor device die, adhesively coupled to the die pad, and electrically coupled to the electrical contact. ### Claim 5 (depends on 2) The semiconductor device package of claim 2 wherein the electrical contact further comprises: a third exposed surface substantially parallel to the first major surface extending to an end flush with the first portion of the side surface, wherein the third exposed surface and the second exposed surface are connected at a second bend in the electrical contact. ### Claim 6 (depends on 5) The semiconductor device package of claim 5, wherein a length of the electrical contact from the first bend to the second bend is less than or equal to two-thirds of a distance between the first and second major surfaces. ### Claim 7 (depends on 5) The semiconductor device package of claim 5, wherein a length of the electrical contact from the second bend to the end of the electrical contact is 0.1 mm. ### Claim 8 A method for forming a semiconductor device package, the method comprising: providing a conductive metal lead frame, wherein the lead frame comprises a die pad configured to mount a semiconductor device die, a plurality of leads wherein each lead of the plurality of leads comprises a first end and a second end wherein the first end is closer to the die pad than the second end, a first length of the lead extending from the first end to a first bend wherein the first bend forms a first angle up from a plane formed by the die pad and the first length of the lead, a second length of the lead extending from the first bend to a second bend wherein the second bend forms a second angle toward the plane formed by the die pad and the first length of the lead, a third length of the lead extending from the second bend to a third bend wherein the third bend forms a third angle, a fourth length of the lead extending from the third bend to the plane formed by the die pad and the first length of the lead, and a fifth length of the lead extending from a fourth bend along the plane formed by the die pad and the first length of the lead wherein the fifth length of the lead and the fourth length of the lead are coupled at the fourth bend. ### Claim 9 (depends on 8) The method of claim 8 further comprising: coating a bottom surface of each of the plurality of leads with a solderable surface, wherein a top surface of each lead is a surface in the direction of the first bend and the bottom surface is a surface opposite the top surface. ### Claim 10 (depends on 9) The method of claim 9 wherein said coating comprises plating, and the solderable surface comprises one or more of tin, gold, silver, palladium and nickel and the conductive metal of the lead frame comprises copper. ### Claim 11 (depends on 9) The method of claim 9 further comprising: mounting one or more semiconductor device die on the die pad; and electrically coupling a contact of one of the one or more semiconductor device die to a lead of the plurality of leads. ### Claim 12 (depends on 11) The method of claim 11 wherein said electrically coupling comprises forming a wire bond from the contact of the one of the one or more semiconductor device die to the lead of the plurality of leads. ### Claim 13 (depends on 11) The method of claim 11 further comprising: placing the lead frame on a mold chase, wherein the bottom surface of the lead frame is in contact with the surface of the mold chase, and the mold chase comprises one or more features configured to conform to the bottom surface of the region of each lead that comprises the second, third, and fourth lengths and the first, second, third, and fourth bends. ### Claim 14 (depends on 13) The method of claim 13 further comprising: forming an encapsulant over and around sides of the one or more semiconductor device die and over and around the lead frame, wherein the mold chase prevents encapsulant from forming along at least the bottom surface of the plurality of leads. ### Claim 15 (depends on 14) The method of claim 14 further comprising: singulating the semiconductor device package from a neighboring semiconductor device by cutting through the encapsulant in a location along the third length of a set of leads of the plurality of leads along a corresponding edge of the semiconductor device package.