# US 2014/0151862 A1 · Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151862 A1 - Document ID: US20140151862A1 - Status: Published application - Kind: A1 - Application number: 14/151,917 - Filed: 2014-01-10 - Published: 2014-06-05 - Earliest claimed: 2012-07-18 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Joachim Mahler; Edward Fuergut; Khalil Hosseini; Georg Meyer-Berg - Web page: https://patentgrep.com/patent/US20140151862A1 ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 74/014: {using batch processing} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/07331: {Connecting techniques} - H10W 72/07336: {Soldering or alloying} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/10: characterised by their shape or disposition - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. ## Claims ### Claim 1 An embedded cackage comprising: at least one chip arranged over a chip carrier, the at least one chip comprising a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. ### Claim 2 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the at least one chip comprises a power semiconductor chip. ### Claim 3 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the chip carrier comprises an electrically conductive leadframe. ### Claim 4 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the plurality of chip contact pads comprise electrically conductive pads. ### Claim 5 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the encapsulation material comprises an electrically insulating material. ### Claim 6 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the encapsulation material electrically insulates the plurality of electrical interconnects from each other. ### Claim 7 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the encapsulation material is formed over the chip and on one or more sidewalls of the at least one chip. ### Claim 8 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the plurality of electrical interconnects are formed over at least one of the at least one chip and the chip carrier. ### Claim 9 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the encapsulation material comprises an electrically insulating laminate. ### Claim 10 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the encapsulation material comprises an electrically insulating laminate comprising at least one from the following group of materials, the group consisting of: filled or unfilled epoxy, pre-impregnated composite fibers, reinforced fibers, laminate, a mold material, a thermoset material, a thermoplastic material, filler particles, fiber-reinforced laminate, fiber-reinforced polymer laminate, fiber-reinforced polymer laminate with filler particles. ### Claim 11 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the structure increases the creepage distance, measured along the surface of the encapsulation material, between the electrical interconnects. ### Claim 12 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the structure comprises a cavity formed in the encapsulation material. ### Claim 13 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the structure comprises further material formed over at least one of the chip and the chip carrier, the further material having a higher dielectric strength than the encapsulation material. ### Claim 14 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the structure comprises a cavity formed in the encapsulation material between the electrical interconnects, and wherein further material at least partially fills the cavity, the further material having a higher dielectric strength than the encapsulation material. ### Claim 15 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the structure comprises a cavity formed in the encapsulation material between the electrical interconnects, and wherein further material at least partially fills the cavity, the further material comprising at least one material from the following group of materials, the group of materials consisting of: glass, ceramics. ### Claim 16 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the structure comprises a cavity formed in the encapsulation material between the electrical interconnects, and wherein further material at least partially fills the cavity forming a protrusion of the further material from the encapsulation material. ### Claim 17 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the structure is formed over at least one of the chip and the chip carrier. ### Claim 18 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the plurality of electrical interconnects are deposited in one or more holes formed in the encapsulation material, each hole releasing an electrical contact electrically connected to a chip contact pad. ### Claim 19 (depends on 1) The embedded integrated circuit package according to claim 1, wherein a first electrical interconnect is electrically connected to a first chip contact pad formed on a first chip side; and wherein a second electrical interconnect is electrically connected to a second chip contact pad formed on the first chip side or a second chip side, wherein the second chip side is formed on the chip carrier. ### Claim 20 (depends on 1) The embedded integrated circuit package according to claim 1, further comprising a first electrical interconnect electrically connected to a first chip contact pad formed on a first chip side; a second electrical interconnect electrically connected to a second chip contact pad is formed on the first chip side; and a third electrical interconnect electrically connected to a third chip contact pad formed on a second chip side via the chip carrier, wherein the second chip side is formed on the chip carrier. ### Claim 21 (depends on 1) The embedded integrated circuit package according to claim 1, wherein the embedded integrated circuit package comprises a wafer level package. ### Claim 22 A method for manufacturing an embedded integrated circuit package, the method comprising: arranging a chip over a chip carrier, the chip comprising a plurality of chip contact pads; forming encapsulation material over the chip carrier and at least partially surrounding the chip; forming a plurality of electrical interconnects through the encapsulation material, thereby electrically connecting each electrical interconnect to a chip contact pad; and forming a structure between the electrical interconnects of the embedded integrated circuit package wherein the structure increases the creepage resistance between the electrical interconnects. ### Claim 23 (depends on 22) The method according to claim 22, wherein arranging a chip over a chip carrier comprises soldering a chip onto a chip carrier. ### Claim 24 (depends on 22) The method according to claim 22, wherein forming encapsulation material over the chip carrier and at least partially surrounding the chip comprises laminating the encapsulation material over the chip and at least part of the chip carrier. ### Claim 25 (depends on 21) The method according to claim 21, wherein forming a plurality of electrical interconnects through the encapsulation material, comprises depositing the electrical interconnects by galvanic electroplating.