# US 2014/0151856 A1 · Chip Module, an Insulation Material and a Method for Fabricating a Chip Module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151856 A1 - Document ID: US20140151856A1 - Status: Published application - Kind: A1 - Application number: 13/693,205 - Filed: 2012-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Ralf Otremba; Josef Hoeglauer; Juergen Schredl; Xaver Schloegel; Klaus Schiess - Web page: https://patentgrep.com/patent/US20140151856A1 ## CPC - H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) - H10W 40/10: Arrangements for heating - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 74/01: Manufacture or treatment - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈r and the thermal conductivity λ of the insulation layer satisfy the condition λ·∈r<4.0 W·m−1·K−1. ## Claims ### Claim 1 A chip module, comprising: a semiconductor chip; a carrier, wherein the semiconductor chip is arranged on or embedded inside the carrier; and an insulation layer at least partly covering a face of the carrier, wherein a dielectric constant ∈r and a thermal conductivity λ of the insulation layer satisfy the condition λ·∈r<4.0 W·m−1·K−1. ### Claim 2 (depends on 1) The chip module according to claim 1, wherein the dielectric constant ∈r and the thermal conductivity λ of the insulation layer satisfies λ·∈r<1.0 W·m−1·K−1. ### Claim 3 (depends on 1) The chip module according to claim 1, wherein the insulation layer comprises a porous material. ### Claim 4 (depends on 3) The chip module according to claim 3, wherein the porosity of the porous material is greater than 50%. ### Claim 5 (depends on 1) The chip module according to claim 1, wherein the insulation layer comprises at least one material selected from the group consisting of undoped silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, polymeric dielectric, nitride and metal oxide. ### Claim 6 (depends on 1) The chip module according to claim 1, wherein the dielectric constant ∈r of the insulation layer is lower than 2.0. ### Claim 7 (depends on 1) The chip module according to claim 1, wherein the thermal conductivity λ of the insulation layer is larger than 1.0 W·m−1·K−1. ### Claim 8 (depends on 1) The chip module according to claim 1, wherein the insulation layer has a thickness that is less than 10 μm. ### Claim 9 (depends on 1) The chip module according to claim 1, wherein the carrier is ceramic or metallic. ### Claim 10 (depends on 1) The chip module according to claim 1, further comprising a through hole for attaching the chip module to an external heat sink, wherein the through hole extends through the carrier and the insulation layer. ### Claim 11 (depends on 1) The chip module according to claim 1, further comprising a heat sink arranged on a surface of the insulation layer, the surface opposite a surface facing the carrier. ### Claim 12 (depends on 1) The chip module according to claim 1, wherein the semiconductor chip comprises at least one of a power integrated circuit, an AC/DC or DC/DC converter circuit, a power MOS transistor, a power Schottky diode, a vertical transistor structure or an insulated gate bipolar transistor. ### Claim 13 A chip module, comprising: a semiconductor chip; a carrier, wherein the semiconductor chip is arranged on or embedded inside the carrier; and an insulation layer at least partly covering a face of the carrier, wherein the insulation layer comprises porous material. ### Claim 14 An insulation material having a dielectric constant ∈r and a thermal conductivity λ which satisfy the condition λ·∈r<4.0 W·m−1·K−1. ### Claim 15 (depends on 14) The insulation material according to claim 14, wherein the dielectric constant ∈r and the thermal conductivity λ satisfy <2.0 W·m−1·K−1. ### Claim 16 (depends on 14) The insulation material according to claim 14, wherein the material is a porous material. ### Claim 17 (depends on 16) The insulation material according to claim 16, wherein the porosity of the material is larger than 60%. ### Claim 18 (depends on 14) The insulation material according to claim 14, wherein the insulation material comprises at least one of silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, polymeric dielectric, nitride or metal oxide. ### Claim 19 (depends on 14) The insulation material according to claim 14, wherein the dielectric constant ∈r is lower than 1.5. ### Claim 20 (depends on 14) The insulation material according to claim 14, wherein the thermal conductivity λ is larger than 1.0 W·m−1·K−1. ### Claim 21 A substrate for carrying electrical components, the substrate comprising an insulation material having a dielectric constant ∈r and a thermal conductivity λ which satisfy the condition λ·∈r<4.0 W·m−1·K−1. ### Claim 22 (depends on 21) The substrate according to claim 21, further comprising a substrate base material, wherein the insulation material has been applied to a surface of the substrate base material. ### Claim 23 A method for fabricating a chip module, the method comprising: providing a carrier; providing a semiconductor chip; arranging the semiconductor chip on or embedding the semiconductor chip inside the carrier; providing an insulation material, wherein a dielectric constant ∈r and a thermal conductivity λ of the insulation material satisfy the condition λ·∈r<4.0 W·m−1·K−1; and applying the insulation material to form an insulation layer that at least partly covers a face of the carrier. ### Claim 24 (depends on 23) The method according to claim 23, wherein the insulation layer is provided as a porous material having porosity larger than 25%. ### Claim 25 (depends on 23) The method according to claim 23, wherein the insulation material is provided having the dielectric constant ∈r and the thermal conductivity λ satisfying <3.0 W·m−1·K−1. ### Claim 26 (depends on 23) The method according to claim 23, wherein applying the insulation layer comprises forming as a film or depositing the insulating layer or forming the insulation layer using etch, UV curing, vapor deposition or spin-on processes.