# US 2014/0151855 A1 · Wafer with Recessed Plug

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- Number: US 2014/0151855 A1
- Document ID: US20140151855A1
- Status: Published application
- Kind: A1
- Application number: 14/173,383
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2011-04-14
- Assignees: Robert Bosch GmbH
- Applicants: Robert Bosch GmbH
- Inventors: Andrew B. Graham; Gary Yama; Gary O'Brien
- Web page: https://patentgrep.com/patent/US20140151855A1

## CPC

- B81B 7/00: Microstructural systems {; Auxiliary parts of microstructural devices or systems}
- B81C 1/00126: {Static structures not provided for in groups B81C1/00031 - B81C1/00119}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- B81B 2203/0307: Anchors
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one embodiment, a method of forming a plug includes providing a base layer, providing an intermediate oxide layer above an upper surface of the base layer, providing an upper layer above an upper surface of the intermediate oxide layer, etching a trench including a first trench portion extending through the upper layer, a second trench portion extending through the oxide layer, and a third trench portion extending into the base layer, depositing a first material portion within the third trench portion, depositing a second material portion within the second trench portion, and depositing a third material portion within the first trench portion.

## Claims

### Claim 1

A wafer comprising:
a base layer;
an intermediate oxide layer above an upper surface of the base layer;
an upper layer above an upper surface of the intermediate oxide layer;
a trench including a first trench portion extending through the upper layer, a second trench portion extending through the oxide layer, and a third trench portion extending only partially into the base layer; and
a plug, the plug including
a first material portion deposited within the third trench portion;
a second material portion deposited within the second trench portion; and
a third material portion deposited within the first trench portion.

### Claim 2 (depends on 1)

The wafer of claim 1, further comprising:
a fourth trench portion within the oxide layer and directly below an un-etched area of the upper layer, wherein the plug further comprises:
a fourth material portion deposited within the fourth trench portion.

### Claim 3 (depends on 2)

The wafer of claim 2, wherein the intermediate oxide layer is a silicon oxide layer.

### Claim 4 (depends on 1)

The wafer of claim 1, further comprising:
a fifth trench portion within the base layer and directly below an un-etched area of the oxide layer.

### Claim 5 (depends on 4)

The wafer of claim 4, wherein the base layer is a silicon substrate

### Claim 6 (depends on 1)

The wafer of claim 1, further comprising:
a fifth trench portion within the base layer;
a sixth trench portion within the oxide layer and directly below an un-etched area of the upper layer;
a fourth material portion located within the fifth trench portion; and
a fifth material portion located within the sixth trench portion, wherein
the fifth and sixth trench portions are straight below the un-etched area of the upper layer, and
the maximum width of the combined first material and fourth material within the base layer, and the maximum width of the combined second material and fifth material within the intermediate oxide layer, are greater than the maximum width of the third material within the upper layer when viewed in cross section.

### Claim 7 (depends on 1)

The wafer of claim 1, wherein the first material portion, the second material portion, and the third material portion comprise silicon nitride.

### Claim 8 (depends on 1)

The wafer of claim 1, wherein at least a portion of an outermost surface of the second material portion is not in contact with the intermediate oxide layer.