# US 2014/0151852 A1 · Bipolar junction transistors with reduced base-collector junction capacitance

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- Number: US 2014/0151852 A1
- Document ID: US20140151852A1
- Status: Published application
- Kind: A1
- Application number: 13/705,717
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corp
- Inventors: James W. Adkisson; James R. Elliott; David L. Harame; Marwan H. Khater; Robert K. Leidy; Qizhi Liu; John J. Pekarik
- Web page: https://patentgrep.com/patent/US20140151852A1

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 10/00: Bipolar junction transistors [BJT]
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/441: {having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body}
- H10D 10/861: {having an emitter region comprising one or more non-monocrystalline elements of Group IV, e.g. amorphous silicon}
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 10/031: {of Schottky BJTs}
- H10D 10/054: {Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions}
- H10D 62/136: {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

## Claims

### Claim 1

A method of fabricating a bipolar junction transistor, the method comprising:
forming a collector region in a substrate comprised of a first semiconductor material that is single crystal;
forming an intrinsic base layer on the collector region;
using a first etching process, forming a trench having a first section extending through the intrinsic base layer and a second section extending into the collector region; and
etching the collector region adjacent to the second section of the trench with a second etching process that etches different crystallographic directions of the first semiconductor material of the substrate at different etch rates.

### Claim 2 (depends on 1)

The method of claim 1 wherein the first etching process is a reactive ion etching process, and the first and second sections of the trench each have sidewalls aligned perpendicular to a top surface of the collector region before the second etching process.

### Claim 3 (depends on 2)

The method of claim 2 wherein the second etching process is selective to a second semiconductor material comprising the intrinsic base layer such that the sidewalls of the first section of the trench are oriented perpendicular to the top surface of the collector region after the second etching process.

### Claim 4 (depends on 3)

The method of claim 3 further comprising:
forming an emitter coupled with the intrinsic base layer and separated from the collector region by the intrinsic base layer.

### Claim 5 (depends on 2)

The method of claim 2 wherein the sidewalls of the second section of the trench are oriented relative to a first crystallographic plane of the first semiconductor material of the substrate after the first etching process, and the sidewalls of the second section of the trench are oriented relative to a second crystallographic plane of the first semiconductor material of the substrate after the second etching process.

### Claim 6 (depends on 2)

The method of claim 2 wherein the sidewalls of the second section of the trench are inclined at an angle relative to the top surface of the collector region after the second etching process.

### Claim 7 (depends on 6)

The method of claim 6 wherein etching the collector region adjacent to the second section of the trench with the second etching process comprises:
partially removing the collector region such that the intrinsic base layer is undercut at the intersection of the sidewalls of the second section of the trench and the intrinsic base layer.

### Claim 8 (depends on 1)

The method of claim 1 wherein etching the collector region adjacent to the second section of the trench with the second etching process comprises:
applying a solution comprising tetra-methyl-ammonium hydroxide (TMAH), potassium hydroxide (KOH), ammonium hydroxide (NH4OH), or ethylenediamine pyrocatechol (EDP) as an etchant for the second etching process.

### Claim 9 (depends on 1)

The method of claim 1 further comprising:
orienting the substrate prior to the first etching process so that the first and second sections of the trench formed by the first etching process have sidewalls aligned with one of the different crystallographic directions.

### Claim 10 (depends on 1)

The method of claim 1 further comprising:
after the second etching process, depositing an electrical insulator to form an isolation region in the first and second sections of the trench.

### Claim 11 (depends on 10)

The method of claim 10 wherein the isolation region includes a void unfilled by the electrical insulator.

### Claim 12 (depends on 1)

The method of claim 1 wherein the second section of the trench includes sidewalls bordered by the collector region, and further comprising:
forming an isolation region surrounding the collector region,
wherein a portion of the collector region is laterally positioned between the sidewalls of the second section of the trench and the isolation region.

### Claim 13 (depends on 1)

The method of claim 1 wherein forming the collector region in the substrate comprises:
selectively implanting ions into the substrate to dope the first semiconductor material in a portion of the substrate with a conductivity type.

### Claim 14

A device structure for a bipolar junction transistor, the device structure comprising:
a collector region;
an intrinsic base on the collector region;
an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base; and
a first isolation region extending through the intrinsic base to the collector region, the first isolation region having a first section with a plurality of first sidewalls extending through the intrinsic base and a second section with a plurality of second sidewalls extending into the collector region, and the second sidewalls inclined relative to the first sidewalls.

### Claim 15 (depends on 14)

The device structure of claim 14 wherein the collector region has a top surface, the first sidewalls of the first isolation region are aligned perpendicular to the top surface of the collector region, and the second sidewalls of the first isolation region are inclined at an angle relative to the top surface of the collector region.

### Claim 16 (depends on 14)

The device structure of claim 14 wherein the collector region is comprised of a single-crystal semiconductor material, and the second sidewalls of the first isolation region are parallel to a crystallographic plane of the single-crystal semiconductor material of the collector region.

### Claim 17 (depends on 14)

The device structure of claim 14 wherein the intrinsic base has a first surface coextensive with the collector region and a second surface coupled with the emitter, and the second surface has a surface area that is larger than a surface area of the first surface.

### Claim 18 (depends on 14)

The device structure of claim 14 wherein the collector region is comprised of a first semiconductor material that is single crystal, and the intrinsic base is comprised of a second semiconductor material that etches at a significantly lower etch rate in an etchant solution comprising tetra-methyl-ammonium hydroxide (TMAH), potassium hydroxide (KOH), ammonium hydroxide (NH4OH), or ethylenediamine pyrocatechol (EDP) than the first semiconductor material.

### Claim 19 (depends on 14)

The device structure of claim 14 wherein the first isolation region is comprised of an electrical insulator, and includes a void unfilled by the electrical insulator.

### Claim 20 (depends on 14)

The device structure of claim 14 wherein the intrinsic base includes a raised region coextensive with the collector region, the first isolation region extends through the raised region of the intrinsic base into the collector region, and further comprising:
an extrinsic base separated from the collector by the intrinsic base; and
a semiconductor layer on the raised region of the intrinsic base, the semiconductor layer physically linking the extrinsic base and the intrinsic base.

### Claim 21 (depends on 14)

The device structure of claim 14 further comprising:
a second isolation region surrounding the collector region, the second isolation region separated from the first isolation region by a portion of the collector region.

### Claim 22 (depends on 14)

The device structure of claim 14 wherein the collector region is comprised of a single-crystal semiconductor material having a conductivity type.

### Claim 23

A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a bipolar junction transistor, the HDL design structure comprising:
a collector region;
an intrinsic base on the collector region;
an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base; and
a first isolation region extending through the intrinsic base to the collector region, the first isolation region having a first section with a plurality of first sidewalls extending through the intrinsic base and a second section with a plurality of second sidewalls extending into the collector region, and the second sidewalls inclined relative to the first sidewalls.

### Claim 24 (depends on 23)

The HDL design structure of claim 23 wherein the HDL design structure comprises a netlist.

### Claim 25 (depends on 23)

The HDL design structure of claim 23 wherein the DHL design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

### Claim 26 (depends on 23)

The HDL design structure of claim 23 wherein the HDL design structure resides in a programmable gate array.