# US 2014/0151851 A1 · Tapered via and mim capacitor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151851 A1
- Document ID: US20140151851A1
- Status: Published application
- Kind: A1
- Application number: 14/176,460
- Filed: 2014-02-10
- Published: 2014-06-05
- Earliest claimed: 2011-04-28
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: JAMES STUART DUNN; ZHONG-XIANG HE; ANTHONY KENDALL STAMPER
- Web page: https://patentgrep.com/patent/US20140151851A1

## CPC

- H10D 1/68: Capacitors having no potential barriers
- H01G 4/228: Terminals
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- Y10T 29/43: Electric condenser making
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

## Claims

### Claim at position 1

1-13. (canceled)

### Claim 14

A method comprising:
selecting an insulating substrate having an upper surface and having a first wire in said insulating substrate;
forming a first insulating layer over said upper surface of said insulating substrate and over said first wire;
forming a first tapered opening in said first insulating layer over said first wire exposing said upper surface of said first wire;
forming a bottom electrode of a capacitor on said first insulating layer;
forming a first conductor over said upper surface of said first wire, said first tapered opening and said first insulating layer to said bottom electrode;
forming a second insulating layer over said bottom electrode; and
forming a top electrode of said capacitor on said second insulating layer positioned over said bottom electrode, said top electrode having a periphery interior of a periphery of said bottom electrode.

### Claim 15 (depends on 14)

The method of claim 14 further comprising:
forming a third insulating layer over said second insulating layer and said top electrode;
a second wire embedded in said third insulating layer over said top electrode; and
forming a plurality of vias formed in said third insulating layer extending from said second wire to an upper surface of said top electrode of said capacitor.

### Claim 16

An apparatus comprising:
an insulating substrate having an upper surface and having a first wire in said insulating substrate;
a first insulating layer over said upper surface of said insulating substrate and over said first wire;
a first tapered opening in said first insulating layer over said first wire exposing an upper surface of said first wire;
a first conductor over said first tapered opening and in said upper surface of said first insulating layer to a bottom electrode of a capacitor, said bottom electrode in said first insulating layer;
a second insulating layer over said bottom electrode;
a top electrode of said capacitor on said second insulating layer positioned above said bottom electrode, said top electrode having a periphery interior of said bottom electrode;
a third insulating layer over said second insulating layer and said top electrode;
a second wire embedded in said third insulating layer positioned over said top electrode; and
a plurality of vias formed in said third insulating layer extending from said second wire to said top electrode of said capacitor.

### Claim 17 (depends on 16)

The apparatus of claim 16 further including a second tapered opening in said first insulating layer over a third wire to expose an upper surface of said third wire; and
a second conductor over said second tapered opening on said third wire and embedded in said first insulating layer to form a fourth wire extending beyond said second tapered opening.

### Claim 18 (depends on 17)

The apparatus of claim 17 wherein said fourth wire and said bottom electrode have substantially the same thickness, said thickness in the range from 0.1 μm to 10 μm.

### Claim 19 (depends on 16)

The apparatus of claim 16 further including a third conductor on said second insulating layer; a fourth wire embedded in said third insulating layer above said third conductor; and
a via extending from said fourth wire to said third conductor.

### Claim 20 (depends on 16)

The apparatus of claim 16 wherein said third conductor and said top electrode have substantially the same thickness, said thickness in the range from 0.1 μm to 10 μm.