# US 2014/0151848 A1 · Mimcap structure in a semiconductor device package

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- Number: US 2014/0151848 A1
- Document ID: US20140151848A1
- Status: Published application
- Kind: A1
- Application number: 14/092,762
- Filed: 2013-11-27
- Published: 2014-06-05
- Earliest claimed: 2012-11-29
- Assignees: Imec
- Applicants: Imec
- Inventors: Mikael Detalle; Eric Beyne
- Web page: https://patentgrep.com/patent/US20140151848A1

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/692: {Electrodes}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10D 1/47: Resistors having no potential barriers
- H10D 86/85: characterised by only passive components
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP is formed between a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.

## Claims

### Claim 1

A semiconductor device package comprising:
one or more semiconductor devices electrically coupled to a metallization stack comprising a plurality of interconnected metallization layers; and
a metal-insulator-metal capacitor (MIMCAP) formed between a lower layer of the metallization layers and an upper layer of the metallization layers, the lower and upper layers being adjacent metallization layers within the stack, wherein the MIMCAP comprises:
at least a portion of a bottom plate which forms a part of the lower metallization layer,
at least a portion of a first conductive layer on and in contact with the bottom plate,
a dielectric layer on and in contact with the first conductive layer,
a second conductive layer on and in contact with the dielectric layer, and
a top plate which forms a part of the upper metallization layer, the top plate being on and in contact with the second conductive layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the first and second conductive layers and the dielectric layer interposed between the first and second conductive layers have substantially the same coverage area and overlap one another when viewed in a direction perpendicular to a lateral plane of the layers.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the first conductive layer laterally extends beyond the areas of coverage covered by the dielectric layer and the second conductive layer.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the first conductive layer is further patterned in an area outside of an area covered by the MIMCAP.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the first conductive layer is patterned to form one or more patterned portions, wherein the patterned portions serve as contact portions for electrical circuit elements.

### Claim 6 (depends on 3)

The semiconductor package of claim 3, wherein the first conductive layer is patterned to form one or more patterned portions, wherein the patterned portions serve as electrical circuit elements formed in at least one of the lower or upper metallization layers.

### Claim 7 (depends on 6)

The semiconductor package of claim 6,
wherein a patterned portion of the first conductive layer forms a resistor in the upper metallization layer, and wherein a stack including a dielectric layer portion and a top conductive layer portion is formed on the resistor,
wherein the dielectric layer portion is formed of the same material and has the same thickness as the dielectric layer of the MIMCAP, and
wherein the top conductive layer portion is formed of the same material and has the same thickness as the second conductive layer of the MIMCAP.

### Claim 8 (depends on 3)

The semiconductor package of claim 3, wherein the second conductive layer is surrounded in a plane of the second conductive layer by a ring structure formed of the same material and having the same thickness as the second conductive layer.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the lower and upper metallization layers form a power supply layer and a ground layer, respectively, of an interposer substrate carrying the one or more integrated circuit devices.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein at least one of the bottom plate and the top plate is provided with perforations formed therethrough, wherein the perforations are at least partially filled with a dielectric material.

### Claim 11

A method of fabricating a semiconductor package, comprising:
forming a first metallization layer by a damascene process, the first metallization layer comprising a bottom plate;
depositing a stack comprising a first conductive layer in contact with the first metallization layer, a dielectric layer and a second conductive layer;
patterning the stack to remove at least portions of the second conductive layer and the dielectric layer, wherein the stack at least partially covers the bottom plate; and
forming a second metallization layer by a damascene process, the second metallization layer comprising a top plate which is on and in contact with the second conductive layer of the stack.

### Claim 12 (depends on 11)

The method of claim 11, wherein patterning the stack comprises forming the stack having each of the first conductive layer, the dielectric layer and the second conductive layer covering substantially the same coverage area and overlapping one another when viewed in a direction perpendicular to a lateral plane of the layers.

### Claim 13 (depends on 11)

The method of claim 11, wherein patterning the stack forms a stack including the dielectric layer and the second conductive layer on the first conductive layer, wherein the first conductive layer remains intact after patterning the stack.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first conductive layer is further patterned in a second patterning process.

### Claim 15 (depends on 14)

The method of claim 14, wherein during the second patterning process, the first conductive layer and the second conductive layer of the stack are patterned simultaneously.

### Claim 16 (depends on 14)

The method of claim 14, wherein during the second patterning process, the second conductive layer of the stack is patterned to form a ring structure around a central portion of the second conductive layer.