# US 2014/0151845 A1 · Semiconductor device having fuse pattern > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151845 A1 - Document ID: US20140151845A1 - Status: Published application - Kind: A1 - Application number: 14/088,654 - Filed: 2013-11-25 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Moon-Gi CHO; Eun-Chul AHN; Sang-Young KIM; Joo-Weon SHIN; Min-Ho LEE - Web page: https://patentgrep.com/patent/US20140151845A1 ## CPC - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - H10W 20/48: Insulating materials thereof - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width. ## Claims ### Claim 1 A semiconductor device comprising: a substrate; a fuse including a first fuse pattern and a second fuse pattern formed at a same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern; and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the opening does not overlap either the first fuse pattern or the second fuse pattern. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first fuse pattern and the second fuse pattern are electrically insulated from each other. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprising an insulating material formed between the first fuse pattern and the second fuse pattern. ### Claim 5 (depends on 4) The semiconductor device of claim 4, further comprising an air gap formed between the first fuse pattern and the insulating material and/or between the second fuse pattern and the insulating material. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the air gap includes a first air gap and a second air gap, the first air gap formed between the first fuse pattern and the insulating material, and the second air gap formed between the second fuse pattern and the insulating material. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising a second insulation layer formed below the first fuse pattern and the second fuse pattern, wherein the second insulation layer includes a trench overlapping the opening. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising a conductive particle formed between the first fuse pattern and the second fuse pattern. ### Claim 9 (depends on 8) The semiconductor device of claim 8, further comprising an air gap formed between the first fuse pattern and the conductive particle and between the second fuse pattern and the conductive particle. ### Claim 10 (depends on 8) The semiconductor device of claim 8, wherein the conductive particle includes materials included in the first and second fuse patterns. ### Claim 11 (depends on 1) The semiconductor device of claim 1, further comprising a first spacer formed between the first fuse pattern and the opening. ### Claim 12 (depends on 11) The semiconductor device of claim 11, further comprising a second spacer formed between the second fuse pattern and the opening, wherein a first air gap is formed between the first spacer and the first fuse pattern. ### Claim 13 (depends on 12) The semiconductor device of claim 12, further comprising a second air gap formed between the second spacer and the second fuse pattern. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein a conductive pattern is not formed immediately above the opening. ### Claim 15 (depends on 1) The semiconductor device of claim 1, further comprising first and second metal wirings formed under the first and second fuse patterns, respectively, the first metal wiring electrically connected to the first fuse pattern through a first via, and the second metal wiring electrically connected to the second fuse pattern through a second via. ### Claim 16 (depends on 1) The semiconductor device of claim 1, further comprising a first metal wiring electrically connected to the first fuse pattern and a second metal wiring electrically connected to the second fuse pattern, wherein the first fuse pattern, the second fuse pattern, the first metal wiring and the second metal wiring are equally spaced apart from the substrate. ### Claim 17 (depends on 1) The semiconductor device of claim 1, further comprising first and second circuit patterns formed below the first and second fuse patterns, respectively, the first fuse pattern electrically connected to the first circuit pattern and the second fuse pattern electrically connected to the second circuit pattern. ### Claim 18 A semiconductor device comprising: a substrate; a first fuse pattern and a second fuse pattern formed on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other; a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening formed between the first fuse pattern and the second fuse pattern; an insulating material formed between the first fuse pattern and the second fuse pattern; and an air gap formed at least between the first fuse pattern and the insulating material. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein a gap between the first fuse pattern and the second fuse pattern is greater than a width of the opening. ### Claim 20 (depends on 18) The semiconductor device of claim 18, wherein the air gap includes a first air gap and a second air gap, the first air gap formed between the first fuse pattern and the insulating material, and the second air gap formed between the second fuse pattern and the insulating material. ### Claim 21 (depends on 18) The semiconductor device of claim 18, further comprising a second insulation layer formed below the first fuse pattern and the second fuse pattern, wherein the second insulation layer includes a trench overlapping the opening. ### Claim 22 (depends on 18) The semiconductor device of claim 18, further comprising a conductive particle formed between the first fuse pattern and the second fuse pattern, the conductive particle surrounded by the insulating material. ### Claim 23 A semiconductor device comprising: a substrate; a fuse including a first fuse pattern and a second fuse pattern formed on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other; and an insulation layer formed on the first fuse pattern and the second fuse pattern, the insulation layer including an opening formed between the first fuse pattern and the second fuse pattern, wherein at least one of the first fuse pattern and the second fuse pattern is undercut below the insulation layer. ### Claim 24 (depends on 23) The semiconductor device of claim 23, further comprising an insulating material formed between the first fuse pattern and the second fuse pattern. ### Claim 25 (depends on 23) The semiconductor device of claim 23, wherein the fuse is a repaired fuse. ### Claim 26 (depends on 23) The semiconductor device of claim 23, wherein the semiconductor device is a memory device. ### Claim 27 A semiconductor device, comprising: a substrate; a first fuse pattern of a fuse and a second fuse pattern of the fuse, formed on the substrate at a same plane, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other; and an insulative pattern formed between and at the same plane as the first fuse pattern and second fuse pattern, wherein the insulative pattern includes at least a first portion formed of a solid material, and at least a second portion that does not permit electrochemical migration of conductive material between the first fuse pattern and the second fuse pattern. ### Claim 28 (depends on 27) The semiconductor device of claim 27, wherein the second portion is formed of air. ### Claim 29 (depends on 28) The semiconductor device of claim 28, further comprising an insulation layer formed on the first fuse pattern and the second fuse pattern, the insulation layer including an opening overlapping the space between the first fuse pattern and the second fuse pattern, wherein the insulation layer overhangs the space between the first fuse pattern and the second fuse pattern. ### Claim 30 (depends on 29) The semiconductor device of claim 29, further comprising a first wiring layer electrically connected to the first fuse pattern and below the insulation layer, a second wiring layer electrically connected to the second fuse pattern and below the insulation layer, and a second insulation layer below each of the first fuse pattern and the second fuse pattern and above the substrate.