# US 2014/0151844 A1 · Integrated circuits separated by through-wafer trench isolation

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- Number: US 2014/0151844 A1
- Document ID: US20140151844A1
- Status: Published application
- Kind: A1
- Application number: 13/705,627
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: NXP B.V.
- Applicants: NXP B. V.
- Inventors: Peter Gerard STEENEKEN; Roel DAAMEN; Gerard KOOPS; Jan SONSKY; Evelyne GRIDELET; Coenraad Cornelis TAK
- Web page: https://patentgrep.com/patent/US20140151844A1

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.

## Claims

### Claim 1

A method of producing an isolated semiconductor circuit on a semiconductor wafer with through trenches, comprising:
providing a semiconductor wafer having the semiconductor circuit and a backend;
applying an etch resistant layer on a surface of the semiconductor wafer opposite the backend;
forming a trench through the semiconductor wafer to the backend;
and
filling the trench with an isolating material.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming a trench includes:
forming a first portion of the trench through a portion of the semiconductor layer; and
forming a second portion of the trench through a remainder of the semiconductor layer and extending to the backend.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first portion of the trench is formed using one of sawing, laser dicing, and etching.

### Claim 4 (depends on 2)

The method of claim 2, wherein the second portion of the trench is formed using etching.

### Claim 5 (depends on 1)

The method of claim 1, wherein the etch resistant layer is metal.

### Claim 6 (depends on 1)

The method of claim 1, wherein the method uses CMOS processes.

### Claim 7 (depends on 1)

The method of claim 1, further comprising dicing the semiconductor wafer to form a plurality of separated semiconductor portions.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming a metallic layer on the etch resistant layer to provide electrical contacts for the semiconductor circuit.

### Claim 9 (depends on 1)

The method of claim 1, wherein the trench has a fishbone pattern on the surface of the semiconductor wafer opposite the backend.

### Claim 10 (depends on 1)

The method of claim 1, wherein the trench defines at least two separated semiconductor portions, each of the semiconductor portions including part of the semiconductor circuit.

### Claim 11

A method of producing an isolated semiconductor circuit on a semiconductor wafer with through trenches, comprising:
providing the semiconductor wafer, the semiconductor wafer having a semiconductor circuit;
depositing a pre-metallic dielectric layer on the semiconductor wafer;
producing a trench through the pre-metallic dielectric layer and into the semiconductor wafer;
filling the trench with a dielectric material;
producing a backend of the semiconductor circuit; and
thinning polishing the wafer so that the trench extends completely through the semiconductor layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising dicing the semiconductor wafer to form a plurality of semiconductor portions.

### Claim 13 (depends on 11)

The method of claim 11, wherein the method uses CMOS processes.

### Claim 14 (depends on 11)

The method of claim 11, wherein the trench defines a fishbone pattern on a surface of the semiconductor wafer opposite the backend.

### Claim 15 (depends on 11)

The method of claim 11, wherein the trench defines an island including the semiconductor circuit.

### Claim 16

A semiconductor circuit comprising:
a first sub-circuit in a first semiconductor portion and a second sub-circuit in a second semiconductor portion;
a backend that includes an electrical connector between the first and second sub-circuits;
a lateral trench including an electrically isolating material, separating the semiconductor portions of the first and second sub-circuits,
wherein the lateral trench extends along a width of the semiconductor portions of the first and second sub-circuits,
wherein one end of the isolating trench is adjacent the backend, and
wherein the isolating trench is filled with an electrically isolating material.

### Claim 17 (depends on 16)

The isolated semiconductor circuit of claim 16, wherein the electrical connector comprises an isolator that prevents direct current flow between the sub-circuits.

### Claim 18 (depends on 17)

The circuit of claim 17, wherein the isolator comprises capacitors made from the backend metals and dielectrics.

### Claim 19 (depends on 16)

The isolated semiconductor circuit of claim 16, wherein the semiconductor circuit is a CMOS circuit.

### Claim 20 (depends on 16)

The isolated semiconductor circuit of claim 16, wherein the laterally isolating trench forms a first island semiconductor portion including the first sub-circuit and a second island semiconductor portion including the second sub-circuit.