# US 2014/0151842 A1 · Semiconductor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151842 A1 - Document ID: US20140151842A1 - Status: Published application - Kind: A1 - Application number: 13/803,200 - Filed: 2013-03-14 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: SK hynix Inc. - Applicants: SK Hynix Inc. - Inventors: Jae Min KIM; Myung Gun PARK - Web page: https://patentgrep.com/patent/US20140151842A1 ## CPC - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 72/865: {Die-attach connectors and bond wires} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor apparatus includes a semiconductor chip formed with cut fuses over one surface thereof; and migration preventing modules preventing occurrence of a phenomenon in which metal ions of the fuses migrate to cut zones of the fuses; each migration preventing module including: a ground electrode formed in the semiconductor chip to face the fuse with a first insulation member interposed therebetween; a floating electrode formed over the fuse with a second insulation member interposed therebetween to face the ground electrode with the fuse interposed therebetween; and a power supply electrode formed over the floating electrode with a third insulation member interposed therebetween. ## Claims ### Claim 1 A semiconductor apparatus comprising: a semiconductor chip formed with cut fuses; and migration preventing modules formed to substantially face the cut fuses, respectively; wherein the each migration preventing module comprising: a ground electrode formed in the semiconductor chip to substantially face the fuse with a first insulation member interposed therebetween; a floating electrode formed over the fuse with a second insulation member interposed therebetween to substantially face the ground electrode with the fuse interposed therebetween; and a power supply electrode formed over the floating electrode with a third insulation member interposed therebetween. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein the semiconductor chip includes a substrate which is formed with semiconductor devices, and a circuit pattern layer which is formed over the substrate and has the one surface of the semiconductor chip as its upper surface, and wherein the circuit pattern layer comprises: bonding pads formed over the one surface of the semiconductor chip; interconnection layers electrically connecting the semiconductor devices with the bonding pads, and the semiconductor devices with the fuses; and an insulation layer insulating and isolating the semiconductor devices from the interconnection layers, the interconnection layers from one another, the interconnection layers from the bonding pads, and the wiring layers from the fuses. ### Claim 3 (depends on 2) The semiconductor apparatus according to claim 2, wherein the ground electrode is formed in the circuit pattern layer, and the first insulation member is constituted by the insulation layer of the circuit pattern layer. ### Claim 4 (depends on 2) The semiconductor apparatus according to claim 2, wherein the third insulation member is constituted by a core of a printed circuit board having a first surface which faces the one surface of the semiconductor chip and a second surface which faces away from the first surface and formed of an insulation substance, and the printed circuit board having connection pads which are electrically connected with the bonding pads, respectively, of the semiconductor chip, wherein the floating electrode and the power supply electrode are formed over the printed circuit board. ### Claim 5 (depends on 4) The semiconductor apparatus according to claim 4, wherein the connection pads are formed over the first surface of the core. ### Claim 6 (depends on 4) The semiconductor apparatus according to claim 4, wherein the core is formed to have an opening which passes through the first surface and the second surface and exposes the bonding pads of the semiconductor chip, and the connection pads are formed over the second surface of the core adjacent to edges of the opening. ### Claim 7 (depends on 4) The semiconductor apparatus according to claim 4, wherein the floating electrode is formed over the first surface of the core. ### Claim 8 (depends on 4) The semiconductor apparatus according to claim 4, wherein the power supply electrode is formed over the second surface to of the core. ### Claim 9 (depends on 8) The semiconductor apparatus according to claim 8, wherein the printed circuit board further includes: external electrodes formed over the second surface of the core; and connection lines formed over the second surface of the core and electrically connecting external electrodes for a power supply voltage among the external electrodes with power supply electrodes. ### Claim 10 (depends on 4) The semiconductor apparatus according to claim 4, wherein the power supply electrode is formed in the core. ### Claim 11 (depends on 10) The semiconductor apparatus according to claim 10, wherein the printed circuit board further includes: external electrodes formed over the second surface of the core; and connection lines formed in the core and electrically connecting external electrodes provided a power supply voltage with power supply electrodes. ### Claim 12 (depends on 4) The semiconductor apparatus according to claim 4, wherein the second insulation member is constituted by an underfill member, wherein the underfill member is formed between the semiconductor chip and the printed circuit board. ### Claim 13 (depends on 4) The semiconductor apparatus according to claim 4, the second insulation member is constituted by an adhesive member, wherein the adhesive member is configured to form between the semiconductor chip and the printed circuit board and attach the semiconductor chip and the printed circuit board to each other. ### Claim 14 (depends on 4) The semiconductor apparatus according to claim 4, wherein the second insulation member is constituted by a portion of a molding part, wherein the molding part is filled between the semiconductor chip and the printed circuit board and formed over the first surface of the core including the semiconductor chip to mold the semiconductor chip. ### Claim 15 (depends on 2) The semiconductor apparatus according to claim 2, wherein the second insulation member is constituted by a first insulation layer, and the third insulation member is constituted by a second insulation layer, wherein the first insulation layer is formed to insulate and isolate the fuses from floating electrodes, cover the one surface of the semiconductor chip including the fuses, and expose portions of the bonding pads, and the second insulation layer is formed over the first insulation layer including the floating electrodes to insulate and isolate the floating electrodes from the power supply electrodes. ### Claim 16 (depends on 15) The semiconductor apparatus according to claim 15, further comprising: first redistribution lines formed over the first insulation layer and electrically connected with the portions of the bonding pads which are exposed through the first insulation layer, wherein the second insulation layer is formed over the first insulation layer including the floating electrodes and the first redistribution lines, and expose portions of the respective first redistribution lines. ### Claim 17 (depends on 16) The semiconductor apparatus according to claim 16, further comprising: second redistribution lines formed over the second insulation layer and electrically connected with the portions of the first redistribution lines which are exposed through the second insulation layer; and connection lines electrically connecting second redistribution lines provided a power supply voltage with the power supply electrodes. ### Claim 18 A semiconductor apparatus, comprising: a cut fuse, wherein the cut fuse includes a anode electrode, a cathode electrode and a cutting portion between the anode electrode and the cathode electrode; and a field applying unit configured to generate an electric field toward the cutting portion. ### Claim 19 (depends on 18) The semiconductor apparatus according to claim 18, wherein a direction of the electric field is perpendicular to an extension direction between the anode electrode and the cathode electrode. ### Claim 20 (depends on 18) The semiconductor apparatus according to claim 18, wherein the field applying unit comprises: a ground electrode formed over the cut fuse to substantially face the cut fuse; a floating electrode formed below the cut fuse to substantially is face the cut fuse; a power electrode configured to selectively coupled to the floating electrode.