# US 2014/0151841 A1 · Semiconductor devices having a positive-bevel termination or a negative-bevel termination and their manufacture

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- Number: US 2014/0151841 A1
- Document ID: US20140151841A1
- Status: Published application
- Kind: A1
- Application number: 14/094,189
- Filed: 2013-12-02
- Published: 2014-06-05
- Earliest claimed: 2012-12-01
- Assignees: North Carolina State University
- Applicants: North Carolina State University
- Inventors: Xing Huang; B. Jayant Baliga; Alex Qin Huang
- Web page: https://patentgrep.com/patent/US20140151841A1

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10D 8/051: {of Schottky diodes}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/8325: {Silicon carbide}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed herein are techniques of manufacturing semiconductor devices having a positive-bevel termination and/or a negative-bevel termination. In a particular example, techniques are disclosed for manufacture of a chip-size SiC device having an orthogonal positive-bevel termination used for the reverse blocking junction. The edge termination may be formed, for example, by cutting across a SiC wafer with a V-shaped dicing tool or blade. The cut may be performed by any suitable dicing tool. The cut may be across a p-n junction for forming positive-bevel termination. Subsequently, a surface of the termination may be etched for removing damage caused by the cutting process.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
providing a wafer having disposed thereon semiconductor layers forming one of a p-n junction and a Schottky barrier junction; and
cutting across the one of the p-n junction and the Schottky barrier junction for forming a substantially orthogonal positive-bevel termination.

### Claim 2 (depends on 1)

The method of claim 1, wherein providing a wafer comprises providing a semiconductor wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the wafer comprises an array of semiconductor devices each having one of a p-n junction and a Schottky barrier junction, and
wherein using the dicing tool comprises using the dicing tool to form a first plurality of cuts across the one of the p-n junctions and the Schottky barrier junction of each of the semiconductor devices in the array.

### Claim 4 (depends on 3)

The method of claim 3, wherein using the dicing tool comprises using the dicing tool to form a second plurality of cuts across the one of the p-n junctions and the Schottky barrier junction of each of the semiconductor devices in the array, wherein the second plurality of cuts are in directions that are substantially orthogonal to the directions of the first plurality of cuts such that the positive-bevel terminal is an orthogonal positive-bevel termination.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first and second plurality of cuts electrically separate the plurality of semiconductor devices from one another.

### Claim 6 (depends on 5)

The method of claim 5, wherein the electrically separated semiconductor devices are one of power semiconductor switches and rectifiers.

### Claim 7 (depends on 3)

The method of claim 3, wherein the semiconductor devices are one of SiC devices and silicon devices.

### Claim 8 (depends on 1)

The method of claim 1, wherein the positive-bevel termination is at a bevel angle that is less than 90°.

### Claim 9 (depends on 1)

The method of claim 1, wherein the dicing tool is one of a V-shaped dicing blade, a V-shaped dicing blade having a flat bottom, a dicing blade with single beveled edge, a wire dicing saw, and a laser dicing system.

### Claim 10 (depends on 1)

The method of claim 1, further comprising etching a surface of the positive-bevel termination for one of removing damage caused by the dicing tool and enlarging the bevel/trench structure to a predetermined depth.

### Claim 11 (depends on 10)

The method of claim 10, wherein etching the surface comprises one of wet etching the surface and dry etching the surface.

### Claim 12 (depends on 10)

The method of claim 10, wherein etching is performed subsequent to using the dicing tool.

### Claim 13 (depends on 1)

The method of claim 1, wherein cutting across the one of the p-n junction and the Schottky barrier junction comprises cutting across the junction such that more material is removed from the edge when progressing from a heavily doped side to a lightly doped side of the p-n junction or a high workfunction side to a low workfunction side of the Schottky barrier.

### Claim 14 (depends on 1)

The method of claim 1, wherein cutting across the one of the p-n junction and the Schottky barrier junction comprises using a dicing tool or saw to cut across the p-n junction or Schottky barrier junction.

### Claim 15 (depends on 1)

The method of claim 1, wherein the dicing tool or saw is one of a blade with two beveled edges like a V-shape or a trapezoidal shape, a blade with single beveled edge and a diamond-coated dicing wire.

### Claim 16 (depends on 1)

The method of claim 1, wherein cutting across the one of the p-n junction and the Schottky barrier junction comprises using a tilted laser beam to cut across the one of the p-n junction and the Schottky barrier junction.

### Claim 17

A semiconductor device being formed on a wafer having disposed thereon semiconductor layers forming one of a p-n junction and a Schottky barrier junction, and comprising a substantially orthogonal positive-bevel termination formed by cutting across the junction.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the wafer is a semiconductor wafer.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the semiconductor device is one of an array of semiconductor devices formed on the wafer and each having one of a p-n junction and a Schottky barrier junction, and
wherein the junctions are terminated with a first plurality of cuts made by the dicing tool cutting across the p-n junctions.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the junctions are terminated with a second plurality of cuts made by the dicing tool cutting across the junctions, wherein the second plurality of cuts are in directions that are substantially orthogonal to the directions of the first plurality of cuts such that the positive-bevel terminal is an orthogonal positive-bevel termination.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein the first and second plurality of cuts electrically separate the plurality of semiconductor devices from one another.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein the separated semiconductor devices are one of power semiconductor switches and rectifiers.

### Claim 23 (depends on 19)

The semiconductor device of claim 19, wherein the semiconductor devices are one of SiC devices and silicon devices.

### Claim 24 (depends on 17)

The semiconductor device of claim 17, wherein the positive-bevel termination is at a bevel angle that is less than 90°.

### Claim 25 (depends on 17)

The semiconductor device of claim 17, wherein the dicing tool is one of a V-shaped dicing blade, a V-shaped dicing blade having a flat bottom, a dicing blade with single beveled edge, a wire dicing saw, and a laser dicing system.

### Claim 26 (depends on 17)

The semiconductor device of claim 17, wherein the positive-bevel termination includes an etched surface.

### Claim 27 (depends on 26)

The semiconductor device of claim 26, wherein the etched surface is formed by one of wet etching and dry etching.

### Claim 28 (depends on 26)

The semiconductor device of claim 26, wherein the etched surface is etched subsequent to cutting across the junction to form the positive-bevel termination.

### Claim 29 (depends on 17)

The semiconductor device of claim 17, wherein the cut is such that more material is removed from the edge when progressing from a heavily doped side to a lightly doped side of the p-n junction or a high workfunction side to a low workfunction side of the Schottky barrier.

### Claim 30 (depends on 17)

The semiconductor device of claim 17, wherein the cut is performed by use of a dicing tool with or without wet/dry etching processes.

### Claim 31

A method of manufacturing a semiconductor device, the method comprising:
providing a wafer having disposed thereon semiconductor device forming a p-n junction; and
cutting across the p-n junction for forming a substantial orthogonal negative-bevel termination.

### Claim 32 (depends on 31)

The method of claim 31, wherein providing a wafer comprises providing a semiconductor wafer.

### Claim 33 (depends on 31)

The method of claim 31, wherein the wafer comprises an array of semiconductor devices each having a p-n junction, and
wherein using the dicing tool comprises using one of a dicing blade, a wire dicing saw, and a tilted layer beam to form a first plurality of cuts across the p-n junctions.

### Claim 34 (depends on 33)

The method of claim 33, wherein using the dicing tool comprises using the dicing tool to form a second plurality of cuts across the p-n junctions, wherein the second plurality of cuts are in directions that are substantially orthogonal to the directions of the first plurality of cuts such that the negative-bevel terminal is a substantially orthogonal negative-bevel termination.

### Claim 35 (depends on 34)

The method of claim 34, wherein the first and second plurality of cuts separate the plurality of semiconductor devices from one another.

### Claim 36 (depends on 35)

The method of claim 35, wherein the separated semiconductor devices are one of power semiconductor switches and rectifiers.

### Claim 37 (depends on 33)

The method of claim 33, wherein the semiconductor devices are one of SiC devices and silicon devices.

### Claim 38 (depends on 31)

The method of claim 31, wherein the negative-bevel termination is at a bevel angle of between about 1° and about 10°.

### Claim 39 (depends on 31)

The method of claim 31, wherein the dicing tool is one of a V-shaped dicing blade having a flat bottom, a blade with single beveled edge, a blade with flat edge, a wire dicing saw, and a tilted laser beam.

### Claim 40 (depends on 41)

The method of claim 41, further comprising etching a surface of the negative-bevel termination for removing damage caused by the dicing tool.

### Claim 41 (depends on 40)

The method of claim 40, wherein etching the surface comprises one of wet etching the surface and dry etching the surface.

### Claim 42 (depends on 40)

The method of claim 40, wherein etching is performed subsequent to using the dicing tool.

### Claim 43 (depends on 31)

The method of claim 31, wherein cutting across the p-n junction comprises cutting across the p-n junction such that more material is removed from the edge when progressing from a lightly doped side to a heavily doped side of the p-n junction.

### Claim 44 (depends on 31)

The method of claim 31, wherein cutting across the p-n junction comprises using a dicing tool to cut across the p-n junction.

### Claim 45 (depends on 31)

The method of claim 31, wherein the negative-bevel termination has an orthogonal angle.

### Claim 46 (depends on 31)

The method of claim 31, wherein the negative-bevel termination has an angle of between about 45° and 135°.

### Claim 47

A semiconductor device being formed on a wafer having disposed thereon semiconductor layers forming a p-n junction, and comprising a negative-bevel termination formed by cutting across the p-n junction.

### Claim 48 (depends on 47)

The semiconductor device of claim 47, wherein the wafer is a semiconductor wafer.

### Claim 49 (depends on 47)

The semiconductor device of claim 47, wherein the semiconductor device is one of an array of semiconductor devices formed on the wafer and each having a p-n junction, and
wherein the p-n junctions are formed with a first plurality of cuts made by the dicing tool cutting across the p-n junctions.

### Claim 50 (depends on 49)

The semiconductor device of claim 49, wherein the p-n junctions are formed with a second plurality of cuts made by the dicing tool cutting across the p-n junctions, wherein the second plurality of cuts are in directions that are substantially orthogonal to the directions of the first plurality of cuts such that the negative-bevel terminal is a substantially orthogonal negative-bevel termination.

### Claim 51 (depends on 50)

The semiconductor device of claim 50, wherein the first and second plurality of cuts separate the plurality of semiconductor devices from one another.

### Claim 52 (depends on 51)

The semiconductor device of claim 51, wherein the separated semiconductor devices are power semiconductor switches or rectifiers.

### Claim 53 (depends on 49)

The semiconductor device of claim 49, wherein the semiconductor devices are one of SiC devices and silicon devices.

### Claim 54 (depends on 47)

The semiconductor device of claim 47, wherein the negative-bevel termination is at a bevel angle of between about 1° and about 10°.

### Claim 55 (depends on 47)

The semiconductor device of claim 47, wherein the dicing tool is one of a V-shaped dicing blade having a flat bottom, a blade with single beveled edge, a blade with flat edge, a wire dicing saw, and a tilted laser beam.

### Claim 56 (depends on 47)

The semiconductor device of claim 47, wherein the negative-bevel termination includes an etched surface.

### Claim 57 (depends on 56)

The semiconductor device of claim 56, wherein the etched surface is formed by one of wet etching and dry etching.

### Claim 58 (depends on 56)

The semiconductor device of claim 56, wherein the etched surface is etched subsequent to cutting across the p-n junction to form the negative-bevel termination.

### Claim 59 (depends on 47)

The semiconductor device of claim 47, wherein the negative-bevel termination is formed by cutting across the p-n junction such that more material is removed from the edge when progressing from a lightly doped side to a heavily doped side of the p-n junction.

### Claim 60 (depends on 47)

The semiconductor device of claim 47, wherein the cut is performed by use of a dicing tool to cut across the p-n junction.

### Claim 61 (depends on 47)

The semiconductor device of claim 47, wherein the corners of negative-bevel termination have orthogonal angles.

### Claim 62 (depends on 47)

The semiconductor device of claim 47, wherein corners of the negative-bevel termination have angles of between about 45° and about 135°.

### Claim 63

A method of manufacturing a semiconductor device, the method comprising:
providing a wafer having disposed thereon semiconductor layers forming a p-n junction; and
cutting across the p-n junction for forming an angled positive-bevel termination.

### Claim 64 (depends on 63)

The method of claim 63, wherein cutting across the p-n junction forms the positive-bevel termination with an angle smaller than 90°.

### Claim 65

A semiconductor device being formed on a wafer having disposed thereon semiconductor layers forming a p-n junction, and comprising an angled positive-bevel termination formed by cutting across the p-n junction.

### Claim 66 (depends on 65)

The semiconductor device of claim 65, wherein the corners of positive-bevel termination have angles of between about 45° and about 135°.