# US 2014/0151838 A1 · Semiconductor device and manufacturing method of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151838 A1 - Document ID: US20140151838A1 - Status: Published application - Kind: A1 - Application number: 14/082,303 - Filed: 2013-11-18 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Koji IIZUKA - Web page: https://patentgrep.com/patent/US20140151838A1 ## CPC - H10F 39/805: {Coatings} - H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12} - H10F 39/024: {of coatings or optical elements} - H10F 39/026: {Wafer-level processing} - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/80: {Constructional details of image sensors} - H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes} - H10F 39/811: {Interconnections} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10F 39/12: Image sensors - H10F 39/8053: {Colour filters} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate having a main surface; an element region where photodetectors are formed in the semiconductor substrate; and a non-element region formed outside the element region over the main surface, the non-element region including: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film, wherein a removed part is formed where the protecting film is removed in at least part of the non-element region. ### Claim 2 (depends on 1) A semiconductor device according to claim 1, wherein the removed part includes a level difference where an upper surface of the flattening film is located on the other side of the upper surface of the top-layer metal wiring opposed to the semiconductor substrate. ### Claim 3 (depends on 1) A semiconductor device according to claim 1, wherein the top-layer metal wiring surrounds the element region in a plan view. ### Claim 4 (depends on 2) A semiconductor device according to claim 2, wherein the removed part includes a first slot which reaches at least a depth of the upper surface of the top-layer metal wiring from the upper surface of the flattening film in part of a region of the level difference. ### Claim 5 (depends on 4) A semiconductor device according to claim 4, wherein the first slot is formed immediately above the top-layer metal wiring. ### Claim 6 (depends on 4) A semiconductor device according to claim 4, wherein the first slot is formed outside the top-layer metal wiring in a plan view. ### Claim 7 (depends on 1) A semiconductor device according to claim 1, wherein the removed part includes a first slot reaching at least the depth of the upper surface of the top-layer metal wiring from an upper surface of the protecting film, and wherein the protecting film extends to an end portion of the main surface. ### Claim 8 (depends on 7) A semiconductor device according to claim 7, wherein the first slot is formed immediately above the top-layer metal wiring. ### Claim 9 (depends on 7) A semiconductor device according to claim 7, wherein the first slot is formed outside the top-layer metal wiring over the main surface. ### Claim 10 (depends on 7) A semiconductor device according to claim 7, wherein the first slot extends, in a plan view, along an edge portion of the element region, and wherein the removed part further includes a second slot, outside the first slot, in a plan view, extending in a direction intersecting with the first slot. ### Claim 11 (depends on 7) A semiconductor device according to claim 7, wherein a film thickness of the protecting film is 0.3 μm or smaller. ### Claim 12 A method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate having a main surface; forming an element region where photodetectors are formed in the semiconductor substrate and a non-element region outside the element region over the main surface; forming a top-layer metal wiring in a top layer of metal wirings formed in the non-element region, a flattening film covering an upper surface of the top-layer metal wiring, and a protecting film formed over the flattening film in the non-element region; and forming a removed part where the protecting film is removed such that the flattening film remains over a surface of the top-layer metal wiring in the non-element region. ### Claim 13 (depends on 12) A method for manufacturing a semiconductor device according to claim 12, wherein the removed part includes a level difference in which an upper surface of the flattening film is located on the other side of the upper surface of the top-layer metal wiring opposed to the semiconductor substrate. ### Claim 14 (depends on 13) A method for manufacturing a semiconductor device according to claim 13, wherein, in the step of forming the removed part, a first slot is formed in part of the region of the level difference so as to reach at least a depth of the upper surface of the top-layer metal wiring from the upper surface of the flattening film. ### Claim 15 (depends on 14) A method for manufacturing a semiconductor device according to claim 14, wherein the first slot is formed immediately above the top-layer metal wiring. ### Claim 16 (depends on 14) A method for manufacturing a semiconductor device according to claim 14, wherein the first slot is formed, in a plan view, outside the top-layer metal wiring. ### Claim 17 (depends on 12) A method for manufacturing a semiconductor device according to claim 12, wherein the removed part includes a first slot reaching at least the depth of the upper surface of the top-layer metal wiring from an upper surface of the protecting film, and wherein the protecting film extends to an end portion of the main surface. ### Claim 18 (depends on 17) A method for manufacturing a semiconductor device according to claim 17, wherein the first slot is formed immediately above the top-layer metal wiring. ### Claim 19 (depends on 17) A method for manufacturing a semiconductor device according to claim 17, wherein the first slot is formed outside the top-layer metal wiring over the main surface. ### Claim 20 (depends on 17) A method for manufacturing a semiconductor device according to claim 17, wherein the first slot extends, in a plan view, along an edge portion of the element region, and wherein, in the step of forming the removed part, a second slot is formed outside the first slot, in a plan view, extending in a direction intersecting with the first slot.