# US 2014/0151819 A1 · Semiconductor Device Having SiGe Substrate, Interfacial Layer and High K Dielectric Layer

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- Number: US 2014/0151819 A1
- Document ID: US20140151819A1
- Status: Published application
- Kind: A1
- Application number: 13/706,081
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, L
- Inventors: Chao-Ching Cheng; Ji-Yin Tsai; Cheng-Hsien Wu; Chih-Hsin Ko; Clement Hsingjen Wann
- Web page: https://patentgrep.com/patent/US20140151819A1

## CPC

- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an interfacial layer. An exemplary structure for a semiconductor device comprises a Si1-xGex substrate, wherein the x is greater than 0.4; a Si layer over the Si1-xGex substrate; and a gate structure disposed over the Si layer, wherein the gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion; wherein the dielectric portion comprises a layer of III-V material on the Si layer and a high-k dielectric layer adjacent to the electrode portion.

## Claims

### Claim 1

A semiconductor device comprising:
a Si1-xGex substrate, wherein the x is greater than 0.4;
a Si layer over the Si1-xGex substrate; and
a gate structure disposed over the Si layer,
wherein the gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion;
wherein the dielectric portion comprises a layer of III-V material on the Si layer and a high-k dielectric layer adjacent to the electrode portion.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the Si layer is from about 1 angstrom to 10 angstroms.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the layer of III-V material is from about 3 angstroms to 10 angstroms.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the III-V material comprises AlP.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the III-V material comprises AlN, AlAs, InP, InN, or InAs.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 further comprises:
an amorphous layer comprising oxygen and the III-V material between the layer of III-V material and the high-k dielectric layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, the high-k dielectric layer is selected from the group consisting of oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the high-k dielectric layer comprises hafnium oxide.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a ratio of a thickness of the high-k dielectric layer to a thickness of the layer of III-V material is from about 1 to about 10.

### Claim 10

A method for fabricating a gate dielectric layer, comprising:
providing a Si1-xGex substrate, wherein the x is greater than 0.4;
forming a Si layer over the Si1-xGex substrate;
forming a dielectric layer of III-V material on the Si layer by a first atomic layer deposition (ALD) process; and
forming a high-k dielectric layer on the dielectric layer of III-V material.

### Claim 11 (depends on 10)

The method of claim 10, wherein a group-V precursor of the first ALD process comprises PH3, NH3, or AsH3.

### Claim 12 (depends on 10)

The method of claim 10, wherein a group-III precursor of the first ALD process comprises Al(CH3)3, Al(CH3CH2)3, or In(CH3)3.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first ALD process comprises injecting a group-V precursor into a reaction chamber at a temperature of about 500° C. to about 600° C.

### Claim 14 (depends on 10)

The method of claim 10, wherein the first ALD process comprises injecting a group-V precursor into a reaction chamber under a pressure of about 250 torr to about 350 torr.

### Claim 15 (depends on 10)

The method of claim 10, wherein the first ALD process comprises injecting a group-III precursor into a reaction chamber at a temperature of about 200° C. to about 300° C.

### Claim 16 (depends on 10)

The method of claim 10, wherein the first ALD process comprises injecting a group-III precursor into a reaction chamber under a pressure of about 3 torr to about 4 torr.

### Claim 17 (depends on 10)

The method of claim 10, wherein the step of forming a high-k dielectric layer is performed using a second ALD process.

### Claim 18 (depends on 17)

The method of claim 17, wherein a metal precursor of the second ALD process comprises metal halide.

### Claim 19 (depends on 18)

The method of claim 18, the metal halide comprises a metal selected from Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

### Claim 20 (depends on 17)

The method of claim 17, wherein an oxygen precursor of the second ALD process comprises O2, O3, or H2O.