# US 2014/0151818 A1 · Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device

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- Number: US 2014/0151818 A1
- Document ID: US20140151818A1
- Status: Published application
- Kind: A1
- Application number: 13/689,936
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Jan Hoentschel; Stefan Flachowsky
- Web page: https://patentgrep.com/patent/US20140151818A1

## CPC

- H10P 30/20: into semiconductor materials, e.g. for doping
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/01336: {on single crystalline silicon, e.g. chemical oxidation using a liquid}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative device disclosed herein includes a gate insulation layer positioned on a semiconducting substrate, wherein the gate insulation layer is comprised of silicon dioxide and a rare earth element, and a silicon-containing gate electrode positioned on the gate insulation layer.

## Claims

### Claim 1

A method of forming a transistor, comprising:
forming a gate insulation layer on a semiconducting substrate;
performing an ion implantation process to implant a rare earth element into said gate insulation layer; and
forming a silicon-containing gate electrode above said gate insulation layer comprising said implanted rare earth element.

### Claim 2 (depends on 1)

The method of claim 1, wherein said rare earth element is one of hafnium, zirconium, lanthanum or tantalum.

### Claim 3 (depends on 1)

The method of claim 1, wherein said ion implantation process is performed at an energy level less than 1 keV.

### Claim 4 (depends on 1)

The method of claim 1, wherein said ion implantation process is performed using a dose of said rare earth element of about 1e13-1e14 atoms/cm2.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming said gate insulation layer comprises performing a thermal oxidation process to form a gate insulation layer comprised of silicon dioxide on said semiconducting substrate.

### Claim 6 (depends on 1)

The method of claim 1, wherein said silicon-containing gate electrode is comprised of polysilicon or amorphous silicon.

### Claim 7 (depends on 1)

The method of claim 1, wherein said gate insulation layer comprising said implanted rare earth element has a k value of 5 or greater.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming said silicon-containing gate electrode comprises:
depositing a layer of silicon-containing material on said gate insulation layer; and
performing an etching process to pattern said layer of silicon-containing material.

### Claim 9 (depends on 1)

The method of claim 1, wherein a concentration of said rare earth element in said gate insulation layer is less than about 1% by volume.

### Claim 10

A method of forming a transistor, comprising:
performing a thermal oxidation process to form a silicon dioxide gate insulation layer on a semiconducting substrate;
performing an ion implantation process to implant a rare earth element into said silicon dioxide gate insulation layer such that said silicon dioxide gate insulation layer comprising said implanted rare earth element has a k value of 5 or greater; and
forming a silicon-containing gate electrode on said gate insulation layer comprising said implanted rare earth element.

### Claim 11 (depends on 10)

The method of claim 10, wherein said rare earth element is one of hafnium, zirconium, lanthanum or tantalum.

### Claim 12 (depends on 10)

The method of claim 10, wherein said silicon-containing gate electrode is comprised of polysilicon or amorphous silicon.

### Claim 13 (depends on 10)

The method of claim 10, wherein forming said silicon-containing gate electrode comprises:
depositing a layer of silicon-containing material on said gate insulation layer; and
performing an etching process to pattern said layer of silicon-containing material.

### Claim 14

A method of forming a transistor, comprising:
performing a thermal oxidation process to form a silicon dioxide gate insulation layer on a semiconducting substrate;
performing an ion implantation process to implant a rare earth element into said gate insulation layer, wherein said ion implantation process is performed using a dose of said rare earth element of about 1e13-1e14 atoms/cm2 and an energy level less than 1 keV; and
forming a silicon-containing gate electrode on said gate insulation layer comprising said implanted rare earth element.

### Claim 15 (depends on 14)

The method of claim 14, wherein said rare earth element is one of hafnium, zirconium, lanthanum or tantalum.

### Claim 16 (depends on 14)

The method of claim 14, wherein said silicon-containing gate electrode is comprised of polysilicon or amorphous silicon.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming said silicon-containing gate electrode comprises:
depositing a layer of silicon-containing material on said gate insulation layer; and
performing an etching process to pattern said layer of silicon-containing material.

### Claim 18 (depends on 14)

The method of claim 14, wherein said gate insulation layer comprising said implanted rare earth element has a k value of 5 or greater.

### Claim 19

A transistor, comprising:
a gate insulation layer positioned on a semiconducting substrate, said gate insulation layer comprising silicon dioxide and a rare earth element, wherein said gate insulation layer has a k value of 5 or greater; and
a silicon-containing gate electrode positioned on said gate insulation layer.

### Claim 20 (depends on 19)

The device of claim 19, wherein said rare earth element is one of hafnium, zirconium, lanthanum or tantalum.

### Claim 21 (depends on 19)

The device of claim 19, wherein said gate insulation layer is a thermally grown layer of silicon dioxide.

### Claim 22 (depends on 19)

The device of claim 19, wherein said silicon-containing gate electrode is comprised of polysilicon or amorphous silicon.

### Claim 23 (depends on 19)

The device of claim 19, wherein a concentration of said rare earth element in said gate insulation layer is less than about 1% by volume.

### Claim 24

A transistor, comprising:
a gate insulation layer positioned on a semiconducting substrate, said gate insulation layer comprising silicon dioxide and a rare earth element, wherein a concentration of said rare earth element in said gate insulation layer is less than about 1% by volume and wherein said gate insulation layer has a k value greater than 5; and
a silicon-containing gate electrode positioned on said gate insulation layer.

### Claim 25 (depends on 24)

The device of claim 24, wherein said silicon-containing gate electrode is comprised of polysilicon or amorphous silicon.

### Claim 26 (depends on 24)

The device of claim 24, wherein said rare earth element is one of hafnium, zirconium, lanthanum or tantalum