# US 2014/0151817 A1 · Self-aligned contacts

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151817 A1
- Document ID: US20140151817A1
- Status: Published application
- Kind: A1
- Application number: 14/174,822
- Filed: 2014-02-06
- Published: 2014-06-05
- Earliest claimed: 2009-12-30
- Assignees: Intel Corporation
- Inventors: Mark T. Bohr; Tahir Ghani; Nadia M. Rahhai-Orabi; Subhash M. Joshi; Joseph M. Steigerwald; Jason W. Klaus; Jack Hwang; Ryan Mackiewicz
- Web page: https://patentgrep.com/patent/US20140151817A1

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/0135: {by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/40: of conductive or resistive materials
- H10P 14/432: {using selective deposition}
- H10P 50/282: {of inorganic materials}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

## Claims

### Claim 1

A transistor comprising:
a substrate;
a pair of spacers on the substrate;
a conformal high-k gate dielectric layer on a surface of the substrate and along sidewalls of the pair of spacers;
a conformal gate electrode layer that is: (a) on the portion of the conformal high-k gate dielectric layer that is on the surface of the substrate and (b) along portions of the conformal high-k gate dielectric layer that are along sidewalls of the pair of spacers;
a fill metal layer on the conformal gate electrode layer;
a cap layer between the pair of spacers and in physical contact with all three of the conformal high-k gate dielectric layer, the conformal gate electrode layer, and the fill metal layer; and
a pair of diffusion regions adjacent to the pair of spacers.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the conformal gate electrode layer comprises a metal selected from the group consisting of hafnium, tantalum, titanium, and nickel.

### Claim 3 (depends on 1)

The transistor of claim 1, further comprising:
a conductive contact disposed on one of the pair of diffusion regions and on a portion of the cap layer.

### Claim 4 (depends on 1)

The transistor of claim 1, further comprising:
a conductive contact disposed on one of the pair of diffusion regions and directly adjacent to one of the pair of spacers.

### Claim 5 (depends on 1)

The transistor of claim 1, further comprising:
a first inter-layer dielectric (ILD) layer disposed directly adjacent to the pair of spacers, the first ILD layer substantially co-planar with the pair of spacers and with the cap layer.

### Claim 6 (depends on 5)

The transistor of claim 5, further comprising:
a second ILD layer disposed on the first ILD layer, on the pair of spacers, and on the cap layer.

### Claim 7 (depends on 6)

The transistor of claim 6, further comprising:
a conductive contact disposed in the first and second ILD layers, the conductive contact disposed on one of the pair of diffusion regions and on a portion of the cap layer.

### Claim 8

A nonplanar transistor comprising:
a FinFET body;
a pair of spacers on the FinFET body;
a conformal gate dielectric layer formed on a surface of the FinFET body between the pair of spacers and formed along sidewalls of the pair of spacers;
a gate electrode formed on the gate dielectric layer and between the pair of spacers, wherein the gate electrode is separated from the pair of spacers by portions of the gate dielectric layer that are formed along the sidewalls of the pair of spacers;
an insulating cap layer on the gate electrode layer between the pair of spacers and directly on the portions of the gate dielectric layer that are formed along the sidewalls of the pair of spacers; and
a pair of diffusion regions adjacent to the pair of spacers.

### Claim 9 (depends on 8)

The nonplanar transistor of claim 8, wherein the gate electrode comprises:
a conformal gate electrode layer that is: (a) on the portion of the conformal gate dielectric layer that is on the surface of the FinFET body between the pair of spacers and (b) along portions of the conformal gate dielectric layer that are along sidewalls of the pair of spacers; and
a fill metal layer on the conformal gate electrode layer.

### Claim 10 (depends on 9)

The nonplanar transistor of claim 9, wherein the conformal gate electrode layer comprises a metal selected from the group consisting of hafnium, tantalum, titanium, and nickel.

### Claim 11 (depends on 8)

The nonplanar transistor of claim 8, further comprising:
a conductive contact disposed on one of the pair of diffusion regions and on a portion of the insulating cap layer.

### Claim 12 (depends on 8)

The nonplanar transistor of claim 8, further comprising:
a conductive contact disposed on one of the pair of diffusion regions and directly adjacent to one of the pair of spacers.

### Claim 13 (depends on 8)

The nonplanar transistor of claim 8, further comprising:
a first inter-layer dielectric (ILD) layer disposed directly adjacent to the pair of spacers, the first ILD layer substantially co-planar with the pair of spacers and with the insulating cap layer.

### Claim 14 (depends on 13)

The nonplanar transistor of claim 13, further comprising:
a second ILD layer disposed on the first ILD layer, on the pair of spacers, and on the insulating cap layer.

### Claim 15 (depends on 14)

The nonplanar transistor of claim 14, further comprising:
a conductive contact disposed in the first and second ILD layers, the conductive contact disposed on one of the pair of diffusion regions and on a portion of the insulating cap layer.