# US 2014/0151816 A1 · Novel contact structure for a semiconductor device and methods of making same

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- Number: US 2014/0151816 A1
- Document ID: US20140151816A1
- Status: Published application
- Kind: A1
- Application number: 13/689,979
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Frank Jakubowski; Juergen Faul
- Web page: https://patentgrep.com/patent/US20140151816A1

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 89/10: Integrated device layouts
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region.

## Claims

### Claim 1

A device, comprising:
first and second spaced-apart active regions formed in a semiconducting substrate;
a layer of gate insulation material positioned on said first active region; and
a first conductive line feature that has a first portion positioned above said layer of gate insulation material and a second portion that conductively contacts said second active region.

### Claim 2 (depends on 1)

The device of claim 1, wherein said first conductive line feature is comprised of polysilicon.

### Claim 3 (depends on 1)

The device of claim 1, wherein said first conductive line feature is comprised of at least one layer of metal and a layer of polysilicon, and wherein one of said at least one layer of metal and said layer of polysilicon conductively contacts said second active region.

### Claim 4 (depends on 1)

The device of claim 1, wherein said first conductive line feature is comprised of a plurality of layers of metal, and wherein at least one of said plurality of layers of metal conductively contacts said second active region.

### Claim 5 (depends on 1)

The device of claim 1, wherein said first conductive line feature is a gate electrode for a pull-up transistor of an SRAM device, wherein said pull-up transistor is formed in and above said first active region.

### Claim 6 (depends on 1)

The device of claim 1, further comprising a third active region that is spaced apart from said first and second active regions, wherein said first conductive line feature is a shared gate electrode for a pull-up transistor and a pull-down transistor of an SRAM device, and wherein said pull-up transistor is formed in and above said first active region and said pull-down transistor in and above said third active region.

### Claim 7 (depends on 1)

The device of claim 1, further comprising a pull-up transistor formed for an SRAM device, wherein said pull-up transistor is formed in and above said second active region, and wherein said pull-up transistor comprises a second conductive line that is a gate electrode for said pull-up transistor.

### Claim 8 (depends on 1)

The device of claim 1, wherein said first conductive line feature has an end surface that is positioned above said second active region, and wherein the device further includes a sidewall spacer formed on said end surface of said first conductive line feature.

### Claim 9 (depends on 1)

The device of claim 1, further comprising a doped source/drain region positioned in said second active region and a contact doped region positioned in said second active region under said second portion of said first conductive line.

### Claim 10 (depends on 1)

The device of claim 1, further comprising a conductive contact that is conductively coupled to an upper surface of said first conductive line feature.

### Claim 11

A device, comprising:
first and second spaced-apart active regions formed in a semiconducting substrate;
a layer of gate insulation material positioned on said first active region;
a first conductive line feature that has a first portion positioned above said layer of gate insulation material and a second portion that conductively contacts said second active region, said first conductive line feature having an end surface that is positioned above said second device region;
a sidewall spacer formed on said end surface of said first conductive line feature;
a doped source/drain region positioned in said second active region; and
a contact doped region positioned in said second active region under said second portion of said first conductive line.

### Claim 12 (depends on 11)

The device of claim 11, wherein said first conductive line feature is a gate electrode for a pull-up transistor of an SRAM device, wherein said pull-up transistor is formed in and above said first active region.

### Claim 13 (depends on 11)

The device of claim 11, further comprising a third active region that is spaced apart from said first and second active regions, wherein said first conductive line feature is a shared gate electrode for a pull-up transistor and a pull-down transistor of an SRAM device, and wherein said pull-up transistor is formed in and above said first active region and said pull-down transistor in and above said third active region.

### Claim 14 (depends on 11)

The device of claim 11, further comprising a pull-up transistor formed for an SRAM device, wherein said pull-up transistor is formed in and above said second active region, and wherein said pull-up transistor comprises a second conductive line that is a gate electrode for said pull-up transistor.

### Claim 15 (depends on 11)

The device of claim 11, further comprising a conductive contact that is conductively coupled to an upper surface of said first conductive line feature.

### Claim 16

An SRAM device, comprising:
first and second spaced-apart active regions formed in a semiconducting substrate;
a first pull-up transistor formed in and above said first active region, said first pull-up transistor comprising a first gate insulation layer;
a first conductive line feature comprised of at least one layer of conductive material, wherein a first portion of said first conductive line feature is positioned above said first gate insulation layer and a second portion of said first conductive line feature conductively contacts said second active region;
a second pull-up transistor formed in and above said second active region, said second pull-up transistor comprising a second gate insulation layer; and
a second conductive line feature comprised of at least one layer of conductive material, wherein a first portion of said second conductive line feature is positioned above said second gate insulation layer and a second portion of said second conductive line feature conductively contacts said first active region.

### Claim 17 (depends on 16)

The device of claim 16, wherein said first and second conductive line features are comprised of polysilicon.

### Claim 18 (depends on 16)

The device of claim 16, wherein said first and second conductive line features are each comprised of at least one layer of metal and a layer of polysilicon, and wherein one of said at least one layer of metal and said layer of polysilicon conductively contacts said second and first active regions, respectively.

### Claim 19 (depends on 16)

The device of claim 16, wherein said first and second conductive line features are comprised of a plurality of layers of metal, and wherein at least one of said plurality of layers of metal conductively contacts said second and first active regions, respectively.

### Claim 20 (depends on 16)

The device of claim 16, further comprising a third active region that is spaced apart from said first and second active regions and a first pull-down transistor of said SRAM device that is formed in and above said third active region, wherein said first conductive line feature is a shared gate electrode for said first pull-up transistor and said first pull-down transistor of said SRAM device.

### Claim 21 (depends on 20)

The device of claim 20, further comprising a fourth active region that is spaced apart from said first and second active regions and a second pull-down transistor of said SRAM device that is formed in and above said fourth active region, wherein said second conductive line feature is a shared gate electrode for said second pull-up transistor and said second pull-down transistor of said SRAM device.

### Claim 22 (depends on 16)

The device of claim 16, further comprising a pull-up transistor formed for an SRAM device, wherein said pull-up transistor is formed in and above said second active region, and wherein said pull-up transistor comprises a second conductive line that is a gate electrode for said pull-up transistor.

### Claim 23 (depends on 16)

The device of claim 16, wherein said first conductive line feature has an end surface that is positioned above said second active region, and wherein the device further includes a sidewall spacer formed on said end surface of said first conductive line feature.

### Claim 24 (depends on 16)

The device of claim 16, further comprising a doped source/drain region positioned in said second active region and a contact doped region positioned in said second active region under said second portion of said first conductive line.

### Claim 25 (depends on 16)

The device of claim 16, further comprising a conductive contact that is conductively coupled to an upper surface of said first conductive line feature.

### Claim 26

A method, comprising:
forming first and second spaced-apart active regions in a semiconducting substrate;
forming a layer of gate insulation material on at least said first and second active regions;
performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region; and
forming a conductive line feature that comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion that conductively contacts said exposed portion of said second active region.

### Claim 27 (depends on 26)

The method of claim 26, wherein forming said layer of gate insulation material comprises forming said layer of gate insulation material from silicon dioxide or a high-k insulating material.

### Claim 28 (depends on 26)

The method of claim 26, wherein said conductive line feature comprises a layer of polysilicon or at least one layer of metal.

### Claim 29 (depends on 26)

The method of claim 26, further comprising, prior to performing said etching process to expose said portion of said second active region, performing an ion implant process to form a doped region in said substrate under said exposed portion of said substrate.

### Claim 30 (depends on 26)

The method of claim 26, wherein forming said conductive line feature comprises forming said conductive line feature by performing a deposition process wherein said conductive line feature is doped in situ with one of a P-type dopant or an N-type dopant.

### Claim 31

A method, comprising:
forming first and second spaced-apart active regions in a semiconducting substrate;
forming a layer of gate insulation material on at least said first and second active regions;
performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region; and
performing an in situ doping deposition process to form a doped polysilicon conductive line feature that is doped with one of an N-type dopant or a P-type dopant, wherein said doped polysilicon conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion that conductively contacts said exposed portion of said second active region.

### Claim 32

A method, comprising:
forming first and second spaced-apart active regions in a semiconducting substrate;
forming a layer of gate insulation material comprised of a high-k insulating material on at least said first and second active regions;
performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region; and
forming a conductive line feature comprised of at least one layer of metal, wherein said conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion wherein said at least one layer of metal conductively contacts said exposed portion of said second active region.

### Claim 33

A method, comprising:
forming first and second spaced-apart active regions in a semiconducting substrate;
forming a layer of gate insulation material comprised of a high-k insulating material on at least said first and second active regions;
performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region; and
forming a conductive line feature comprised of at least one layer of metal and a silicon-containing layer of material positioned above said at least one layer of metal, wherein said conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion wherein said silicon-containing layer of material conductively contacts said exposed portion of said second active region.

### Claim 34 (depends on 33)

The method of claim 33, wherein said silicon-containing layer of material is comprised of polysilicon or amorphous silicon.

### Claim 35

A method, comprising:
forming first and second spaced-apart active regions in a semiconducting substrate;
forming a sacrificial gate structure above said first and second active regions;
forming a sidewall spacer adjacent said sacrificial gate structure;
removing said sacrificial gate structure to thereby define a gate cavity that is laterally defined by inner surfaces of said sidewall spacers;
forming a layer of gate insulation material comprised of a high-k insulating material in said gate cavity on at least said first and second active regions;
performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region; and
forming a conductive line feature comprised of at least one layer of metal within said cavity, wherein said conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion wherein said at least one layer of metal conductively contacts said exposed portion of said second active region.