# US 2014/0151815 A1 · Read-only memory and its manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151815 A1 - Document ID: US20140151815A1 - Status: Published application - Kind: A1 - Application number: 14/130,470 - Filed: 2012-08-02 - Published: 2014-06-05 - Earliest claimed: 2011-09-28 - Assignees: Csmc Technologies Fab2 Co., Ltd. - Inventors: Kai HUANG; Peng DU; Jianxiang CAI; Tsung-nten HSU - Web page: https://patentgrep.com/patent/US20140151815A1 ## CPC - H10B 20/00: Read-only memory [ROM] devices - H10B 20/387: {Source region or drain region doping programmed} - H10D 89/10: Integrated device layouts - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A read-only memory includes a plurality of storage units arranged in an array. The read-only memory includes two kinds of storage units with different structures, the two kinds of storage units with different structures are a first MOS transistor and a second MOS transistor. A source and a drain of the first MOS transistor have the same type, a source and a drain of the second MOS transistor have inverse type. These two kinds of MOS transistors can be used to store binary 0 and 1 respectively. In the manufacturing method of the read-only memory, the same type of drain and source can be manufactured simultaneously, no extra mask plate is needed, so the extra mask plate of a conventional read-only memory can be saved. ## Claims ### Claim 1 A read-only memory, comprising a plurality of storage units arranged in an array, wherein the read-only memory comprises two kinds of storage units with different structures, the two kinds of storage units with different structures are a first MOS transistor and a second MOS transistor, a source and a drain of the first MOS transistor have the same type, a source and a drain of the second MOS transistor have inverse types. ### Claim 2 (depends on 1) The read-only memory according to claim 1, wherein the two kinds of storage units with different structures are P-type storage units, the source and the drain of the first MOS transistor are P-type, the drain of the second MOS transistor is P-type, the source of the second MOS transistor is N-type. ### Claim 3 (depends on 1) The read-only memory according to claim 1, wherein the two kinds of storage units with different structures are N-type storage units, the source and the drain of the first MOS transistor are N-type, the drain of the second MOS transistor is N-type, the source is P-type. ### Claim 4 (depends on 1) The read-only memory according to claim 1, wherein the first MOS transistor and the second transistor are both provided with control gates of their own, the first MOS transistor and the second MOS transistor are both provided with lightly doped drain regions located between the drain and its control gate and between the source and its control gate. ### Claim 5 (depends on 1) A method of manufacturing the read-only memory according to claim 1, the read-only memory comprising storage units and peripheral devices surrounding the storage units, the method comprising: step 1, providing a silicon substrate, forming active regions of the storage units and the peripheral devices on the silicon substrate simultaneously; step 2, forming a gate oxide dielectric and a control gate of the storage units and the peripheral devices on surfaces of the active regions; step 3, forming a source and a drain of a first MOS transistor and a drain or a source of a second MOS transistor of the storage unit, and a source and a drain of the peripheral device on an active region on two sides of the control gate simultaneously, the source of the first MOS transistor and the source or the drain of the second MOS transistor having the same type, the source of the first MOS transistor and the source and the drain of the peripheral device having the same type; and step 4, forming a source and a drain of the second MOS transistor and a source and a drain of the peripheral device on the active region on two sides of the control gate simultaneously, the source of the first MOS transistor and the source or the drain of the second MOS transistor having inverse types, the source of the first MOS transistor and the source and the drain of the peripheral device having inverse types. ### Claim 6 (depends on 5) The method according to claim 5, wherein step 3 comprises: step 31, coating a photoresist on a surface of the silicon substrate with the control gate; step 32, removing photoresists on regions of the drain and the source of the first MOS transistor to be formed, and removing photoresists on regions of the drain or the source of the second MOS transistor to be formed which have the same type with the source of the first MOS transistor and on regions of the drain and the source of the peripheral device simultaneously; step 33, performing an ion implantation to the region which is removed from the photoresist to form a source and a drain; and step 34, removing the photoresist remained on the surface of the silicon substrate after the ion implantation process. ### Claim 7 (depends on 6) The method according to claim 6, wherein step 32 comprises: providing a first drain and source mask plate, defining a region of the drain and the source of the first MOS transistor and a region of the drain or a region of the source of the second MOS transistor which have the same type with the source of the first MOS transistor and a region of the source and the drain of the peripheral device on a first drain and source mask plate; exposing the photoresist located on a surface of the of the silicon substrate with the control gate by using the first drain and source mask plate, developing and removing the photoresist formed on the drain region and the source region defined by the first drain and source mask plate on the surface of the silicon substrate. ### Claim 8 (depends on 5) The method according to claim 5, wherein step 4 comprises: step 41, coating a photoresist on the surface of the silicon substrate with the control gate; step 42, removing the photoresist formed on regions of the source and the drain of the second MOS transistor which has inverse type with the source of the first MOS transistor and the source and drain of the peripheral device; step 43, performing an ion implantation process which has inverse type with the source of the first MOS transistor to a region which is removed from the photoresist to form a source and a drain; and step 44, removing the photoresist remained on the surface of the silicon substrate after the ion implantation. ### Claim 9 (depends on 8) The method according to claim 8, wherein step 42 comprises: providing a second drain and source mask plate, defining a region of the source or drain of the second MOS transistor which has inverse type with the source of the first MOS transistor and a region of the source and the drain of the peripheral device on the second drain and source mask plate; exposing the photoresist located on the surface of the silicon substrate with the control gate by using the second drain and source mask plate, developing and removing the photoresist formed on the drain region and the source region defined by the first drain and source mask plate on the surface of the silicon substrate. ### Claim 10 (depends on 2) The read-only memory according to claim 2, wherein the first MOS transistor and the second transistor are both provided with control gates of their own, the first MOS transistor and the second MOS transistor are both provided with lightly doped drain regions located between the drain and its control gate and between the source and its control gate. ### Claim 11 (depends on 3) The read-only memory according to claim 3, wherein the first MOS transistor and the second transistor are both provided with control gates of their own, the first MOS transistor and the second MOS transistor are both provided with lightly doped drain regions located between the drain and its control gate and between the source and its control gate.