# US 2014/0151814 A1 · Methods for forming fins for metal oxide semiconductor device structures

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- Number: US 2014/0151814 A1
- Document ID: US20140151814A1
- Status: Published application
- Kind: A1
- Application number: 13/996,468
- Filed: 2011-12-21
- Published: 2014-06-05
- Earliest claimed: 2011-12-21
- Assignees: Intel Corporation
- Inventors: Martin D. Giles; Tahir Ghani
- Web page: https://patentgrep.com/patent/US20140151814A1

## CPC

- H10D 86/215: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

## Claims

### Claim 1

A method of fabricating a device, comprising:
forming silicon fins on a substrate;
forming a first dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of the silicon fins are exposed;
epitaxially growing germanium on the upper region of the silicon fins.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the first dielectric layer on the substrate comprises:
depositing the first dielectric layer on the substrate;
recessing the first dielectric layer to expose the upper region of the silicon fins.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
depositing a second dielectric layer on the substrate;
recessing the second dielectric layer to expose an upper surface of the silicon fins;
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the second dielectric layer and upper regions of the germanium.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
depositing a second dielectric layer on the substrate;
recessing the second dielectric layer to expose an upper surface of the silicon fins;

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the second dielectric layer and upper regions of the germanium; and
depositing a third dielectric layer on the substrate.

### Claim 6 (depends on 4)

The method of claim 4, further comprising:
selectively etching the exposed upper surface of the silicon fins to a recessed level below lower regions of the germanium; and
depositing a third dielectric layer on the substrate.

### Claim 7

A method of fabricating a device, comprising:
forming silicon fins on a substrate;
epitaxially growing a layer on the silicon fins;
depositing a first dielectric layer on the substrate;
planarizing the first dielectric layer such that an upper surface of the silicon fins are exposed and an upper surface of the layer is exposed.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the first dielectric layer and upper regions of the layer.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
depositing a second dielectric layer on the substrate.

### Claim 10 (depends on 7)

The method of claim 7, wherein the layer comprises germanium or silicon germanium.

### Claim 11 (depends on 10)

The method of claim 10, wherein the layer comprises germanium fins or silicon germanium fins having a pitch that is approximately one half of a pitch of the silicon fins.

### Claim 12

A method of fabricating a device, comprising:
forming silicon fins on a substrate;
forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper surface of the silicon fins are exposed;
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the dielectric layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
selectively epitaxially growing a layer on the exposed upper surface of the silicon fins.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
planarizing upper regions of the layer and the dielectric layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the layer comprises germanium or silicon germanium.

### Claim 16 (depends on 12)

The method of claim 12, further comprising:
depositing a germanium layer on the exposed upper surface of the silicon fins and the dielectric layer; and
annealing the germanium layer to form crystalline germanium fins.

### Claim 17

A complementary metal oxide semiconductor (CMOS) integrated circuit, comprising:
a n-type metal oxide semiconductor (NMOS) device having a fin with a first height; and
a p-type metal oxide semiconductor (PMOS) device having a germanium fin with a second height and a corresponding silicon fin having a third height.

### Claim 18 (depends on 17)

The CMOS integrated circuit of claim 17, wherein the germanium fin forms a body of the PMOS device.

### Claim 19 (depends on 17)

The CMOS integrated circuit of claim 17, wherein the fin of the NMOS device comprises a silicon fin, wherein the silicon fin forms a body of a NMOS device.

### Claim 20 (depends on 19)

The CMOS integrated circuit of claim 19, wherein the germanium fin has a pitch that is approximately one half of a pitch of the silicon fin of the PMOS device.