# US 2014/0151812 A1 · Contact Plugs in SRAM Cells and the Method of Forming the Same

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- Number: US 2014/0151812 A1
- Document ID: US20140151812A1
- Status: Published application
- Kind: A1
- Application number: 13/691,367
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US20140151812A1

## CPC

- H10W 20/0698: {Local interconnections}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 89/10: Integrated device layouts
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening.

## Claims

### Claim 1

A method comprising:
forming a dielectric layer over a portion of a Static Random Access Memory (SRAM) cell, wherein the SRAM cell comprises:
a first pull-up transistor and a second pull-up transistor;
a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor; and
a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively;
forming and patterning a first mask layer over the dielectric layer, wherein the forming and the patterning of the first mask layer includes:
patterning a photo resist material disposed over the first mask layer; and
etching the first mask layer to transfer a pattern from the patterned photo resist material to the first mask layer;
thereafter, forming a second mask layer over the dielectric layer;
etching the dielectric layer using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer; and
forming a contact plug in the contact opening.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first mask layer comprises a material selected from the group consisting essentially of a silicon oxide based dielectric, silicon oxynitride, silicon nitride, polysilicon, amorphous silicon, a carbon-containing dielectric material, a nitrogen-containing dielectric material, an organic material, a refractory metal, and combinations thereof.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second mask layer comprises a photo resist, and wherein the second mask layer is over the first mask layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein after the step of patterning the first mask layer, the first mask layer forms a continuous layer with a first long contact opening therein, wherein the first long contact opening has a longitudinal direction parallel to a long boundary of the SRAM cell, and wherein the first long contact opening has a length greater than or equal to a length of the long boundary.

### Claim 5 (depends on 4)

The method of claim 4, wherein the continuous layer further comprises a second long contact opening therein, wherein the second long contact opening has a longitudinal direction parallel to a long boundary of the SRAM cell, and wherein the second long contact opening has a length smaller than the length of the long boundary.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second long contact opening extends to a boundary of the SRAM cell.

### Claim 7 (depends on 5)

The method of claim 5, wherein the second long contact opening does not extend to any boundary of the SRAM cell.

### Claim 8 (depends on 1)

The method of claim 1, wherein after the step of patterning the first mask layer, the first mask layer forms islands that are separated from each other.

### Claim 9 (depends on 1)

The method of claim 1, wherein at a time the contact plug is formed, an additional contact plug is formed simultaneous, wherein the contact plug is over and connects to a drain of the first pull-down transistor, and the additional contact plug is over and connects to a drain of the first pull-up transistor, and wherein the contact plug and the additional contact plug are separated from each other.

### Claim 10 (depends on 1)

The method of claim 1, wherein the contact plug continuously extends over, and interconnects, a drain of the first pull-down transistor and a drain of the first pull-up transistor.

### Claim 11

A method comprising:
forming a Static Random Access Memory (SRAM) cell comprising a plurality of gate electrodes, and a plurality of active region strips, wherein the plurality of active region strips form transistors with the plurality of gate electrodes;
forming an Inter-Layer Dielectric (ILD) over the plurality of gate electrodes and the plurality of active region strips;
forming a first mask layer over the ILD, wherein the first hard mask layer covers first portions of the ILD, with second portions of the ILD exposed through openings in the first mask layer, wherein the forming of the first mask layer includes:
forming a resist over the first mask layer;
patterning the resist; and
etching the first mask layer using the patterned resist to form the openings through which the second portions of the ILD are exposed;
forming a second mask layer, wherein the second mask layer comprises portions filled into parts of the openings in the first mask layer;
etching the ILD using the first mask layer and the second mask layer as an etching mask to form a plurality of contact openings in the ILD; and
forming a plurality of contact plugs in the plurality of contact openings.

### Claim 12 (depends on 11)

The method of claim 11, wherein the openings in the first mask layer comprise:
a first opening overlapping, and having a longitudinal direction parallel to, a first boundary of the SRAM cell; and
a second opening overlapping, and having a longitudinal direction parallel to, a second boundary of the SRAM cell, wherein the first boundary and the second boundary are parallel to each other, and wherein each of the first opening and the second opening extends from a third boundary of the SRAM cell to a fourth boundary of the SRAM cell, with the third boundary and the fourth boundary perpendicular to the first boundary and the second boundary.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second mask layer comprises strips having longitudinal directions perpendicular to the longitudinal direction of the first opening.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first mask layer comprises a hard mask material, and the second mask layer comprises a photo resist.

### Claim 15 (depends on 11)

The method of claim 11, wherein the step of forming the plurality of contact plugs comprises:
forming a first contact plug over and connected to a drain of a pull-down transistor of the SRAM cell; and
forming a second contact plug over and connected to a drain of a pull-up transistor of the SRAM cell, wherein the method further comprises forming a metal connection over and interconnecting the first contact plug and the second contact plug.

### Claim 16 (depends on 11)

The method of claim 11, wherein the step of forming the plurality of contact plugs comprises forming a contact plug continuously extending over, and interconnecting, a drain of a pull-down transistor of the SRAM cell and a drain of a pull-up transistor of the SRAM cell.

### Claim at position 17

17-23. (canceled)

### Claim 24

A method comprising:
receiving a substrate having a circuit device formed thereupon, wherein the circuit device includes:
a material layer formed on the substrate;
a first masking layer formed on the material layer; and
a photoresist formed on the first masking layer;
patterning the photoresist;
etching the first masking layer to remove a portion of the first masking layer exposed by the patterned photoresist;
forming a second masking layer on the substrate and within a cavity formed by the etching of the first masking layer;
patterning the second masking layer; and
etching the material layer to remove a portion of the material layer exposed by the etched first masking layer and the patterned second masking layer.

### Claim 25 (depends on 24)

The method of claim 24, wherein the circuit device includes an SRAM cell over which the material layer is formed.

### Claim 26 (depends on 24)

The method of claim 24 further comprising:
forming a conductive feature within a recess left by the etching of the material layer.

### Claim 27 (depends on 24)

The method of claim 24 further comprising:
forming a plurality of separate conductive features within a region of the material layer underlying the cavity formed by the etching of the first masking layer.

### Claim 28 (depends on 24)

The method of claim 24, wherein the circuit device defines a standard cell, and wherein the cavity formed by the etching of the first masking layer extends between two boundaries of the standard cell.