# US 2014/0151808 A1 · Bulk finfet esd device

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- Number: US 2014/0151808 A1
- Document ID: US20140151808A1
- Status: Published application
- Kind: A1
- Application number: 13/690,179
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Robert J. Gauthier, Jr.; Tom C. Lee; JunJun Li; Souvick Mitra; Christopher S. Putnam
- Web page: https://patentgrep.com/patent/US20140151808A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 8/01: Manufacture or treatment
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0102: {of thyristors having built-in components, e.g. thyristor having built-in diode}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs}
- H10D 89/611: {using diodes as protective elements}
- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 89/811: {using FETs as protective elements}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

## Claims

### Claim 1

A dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology, comprising:
a bulk silicon substrate;
a shallow trench isolation (STI) region formed over the bulk silicon substrate;
a first ESD device positioned above the STI region; and
a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

### Claim 2 (depends on 1)

The dual ESD protection device of claim 1, wherein the first and second ESD devices include diodes.

### Claim 3 (depends on 2)

The dual ESD protection device of claim 2, wherein the first ESD device forms a pn junction.

### Claim 4 (depends on 2)

The dual ESD protection device of claim 2, wherein the second ESD device forms a pn junction.

### Claim 5 (depends on 1)

The dual ESD protection device of claim 1, wherein the first and second ESD devices include thyristors.

### Claim 6 (depends on 5)

The dual ESD protection device of claim 5, wherein the first ESD device forms a pnpn junction.

### Claim 7 (depends on 5)

The dual ESD protection device of claim 5, wherein the second ESD device forms two pn junctions.

### Claim 8 (depends on 1)

The dual ESD protection device of claim 1, wherein the first and second ESD devices include lateral npn transistors.

### Claim 9 (depends on 8)

The dual ESD protection device of claim 8, wherein the first ESD device forms a npn junction.

### Claim 10 (depends on 8)

The dual ESD protection device of claim 8, wherein the second ESD device forms a npn junction.

### Claim 11

A method of manufacturing a dual ESD protection device in fin field effect transistor (FinFET) process technology, the method comprising:
providing a bulk silicon wafer substrate;
forming a plurality of fins on a top portion of the bulk silicon wafer substrate;
forming an oxide isolation region between each of the fins, the oxide isolation region including a shallow trench isolation (STI);
performing a selective epitaxial growth process to merge a portion of the plurality of fins; and
patterning, etching, and implanting the portion of the plurality of fins to form the dual ESD protection device including: a first ESD device positioned above the oxide isolation region; and a second ESD device positioned below the oxide isolation region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the oxide isolation region.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first and second ESD devices include diodes.

### Claim 13 (depends on 12)

The method of claim 12, wherein the implanting forms a pn junction for the first ESD device.

### Claim 14 (depends on 12)

The method of claim 12, wherein the implanting forms a pn junction for the second ESD device.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first and second ESD devices include thyristors.

### Claim 16 (depends on 15)

The method of claim 15, wherein the implanting forms a pnpn junction for the first ESD device.

### Claim 17 (depends on 15)

The method of claim 15, wherein the implanting forms two pn junctions for the second ESD device.

### Claim 18 (depends on 11)

The method of claim 11, wherein the first and second ESD devices include lateral npn transistors.

### Claim 19 (depends on 18)

The method of claim 18, wherein the implanting forms a npn junction for the first ESD device.

### Claim 20 (depends on 18)

The method of claim 18, wherein the implanting forms a npn junction for the second ESD device.