# US 2014/0151805 A1 · Method for fabricating a connection region in a semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151805 A1
- Document ID: US20140151805A1
- Status: Published application
- Kind: A1
- Application number: 13/888,307
- Filed: 2013-05-06
- Published: 2014-06-05
- Earliest claimed: 2009-02-27
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sang Soo LEE
- Web page: https://patentgrep.com/patent/US20140151805A1

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a buried-type wordline in an active region defined on a SOI substrate, forming a silicon connection region for connecting an upper silicon layer to a lower silicon layer between neighboring buried type wordlines, and recovering the upper silicon layer on the silicon connection region.

## Claims

### Claim at position 1

1-13. (canceled)

### Claim 14

A semiconductor device, comprising:
a buried-type wordline in an active region defined on a SOI substrate;
a silicon connection region, located between neighboring buried type wordlines, configured to connect an upper silicon layer to a lower silicon layer which is separated from the upper silicon layer by a buried insulating layer of the SOI substrate; and
a channel region configured to totally occupy a gap between the buried insulating layer and the buried-type wordline to reduce a leakage current.

### Claim 15 (depends on 14)

The semiconductor device according to claim 14, wherein the silicon connection region transfers a back bias voltage supplied through the lower silicon layer to the upper silicon layer to thereby control a threshold voltage.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, further comprising:
a device isolation layer configured to define the active region in the SOI substrate; and
a source/drain region located at both sides of the buried-type wordline.

### Claim 17 (depends on 16)

The semiconductor device according to claim 16, wherein the channel region transmits a charge between the source/drain region according to a voltage level supplied to the buried-type wordline.

### Claim 18 (depends on 11)

The semiconductor device according to claim 11, wherein a depth of a bottom of the buried-type wordline is about 1000 Å to about 1300 Å and a thickness of the upper silicon layer is about 1400 Å to about 1600 Å.

### Claim 19 (depends on 11)

The semiconductor device according to claim 11, wherein both the silicon connection region and the lower silicon layer include a substantially equivalent material.