# US 2014/0151804 A1 · Semiconductor Device Including a Fin and a Drain Extension Region and Manufacturing Method

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- Number: US 2014/0151804 A1
- Document ID: US20140151804A1
- Status: Published application
- Kind: A1
- Application number: 13/692,462
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Andreas Meiser; Christian Kampen
- Web page: https://patentgrep.com/patent/US20140151804A1

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 86/215: {comprising FinFETs}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/19: {Diffusion sources}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

One embodiment of a semiconductor device includes a fin on a first side of a semiconductor body. The semiconductor device further includes a body region of a second conductivity type in at least a part of the fin. The semiconductor device further includes a drain extension region of a first conductivity type, a source and a drain region of the first conductivity type, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region.

## Claims

### Claim 1

A semiconductor device, comprising:
a fin at a first side of a semiconductor body;
a body region of a second conductivity type in at least a part of the fin;
a drain extension region of a first conductivity type;
a source region and a drain region of the first conductivity type; and
a gate structure adjoining opposing walls of the fin,
wherein the body region and the drain extension region are arranged one after another between the source region and the drain region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the drain extension region has a lateral dimension between 0.5 μm and 100 μm.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a maximum dopant concentration of the drain extension region is less than 1018 cm−3.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the fin includes at least part of the drain extension region.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a shallow trench isolation at a top face of the fin adjoining the drain extension region.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure adjoins the top face of the fin.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the body region includes a first channel portion adjoining a first sidewall of the fin, and wherein a maximum relative variation of the doping concentration in the first channel portion of the body region along a vertical direction perpendicular to the first side of the semiconductor body is less than 20%.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a deep body region of the second conductivity type adjoining a bottom side of the drain extension region, wherein the deep body region is electrically connected to the body region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein a maximum dopant concentration of the deep body region is 1018 cm−3.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor body includes the drain extension region, the deep body region, a first semiconductor layer of the first conductivity type, and a second semiconductor layer of the first conductivity type including a higher doping concentration than the first semiconductor layer, successively arranged along a line perpendicular to the first side of the semiconductor body.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor body includes the drain extension region, the deep body region, a first semiconductor layer of the second conductivity type, and a second semiconductor layer of the first conductivity type including a higher doping concentration than the first semiconductor layer, successively arranged along a line perpendicular to the first side of the semiconductor body.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor body includes the drain extension region, the deep body region, and a buried silicon oxide layer, successively arranged along a line perpendicular to the first side of the semiconductor body.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor body includes one of a p-doped semiconductor layer on an n-doped semiconductor substrate, an n-doped semiconductor layer on a p-doped semiconductor substrate, and a silicon-on-insulator substrate.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein
a first contact trench extends from the first side of the semiconductor body into the source region;
a second contact trench extends from the first side of the semiconductor body into the drain region;
the source region and the drain region include highly doped silicon of the first conductivity type adjoining sidewalls and a bottom side of the first and the second contact trench; and wherein
the first and second contact trenches are filled with a first and a second conductive material.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein
a first contact trench extends from the first side of the semiconductor body into the source region;
a second contact trench extends from the first side of the semiconductor body into the drain region; and wherein
one of the first and second contact trenches extends through a respective one of the source and drain regions.

### Claim 16 (depends on 1)

An integrated circuit comprising the semiconductor device of claim 1.

### Claim 17

A method of manufacturing a semiconductor device, comprising:
forming a fin at a first side of a semiconductor body;
forming a body region of a second conductivity type in at least a part of the fin;
forming a drain extension region of a first conductivity type;
forming a source region and a drain region of the first conductivity type; and
forming a gate structure adjoining opposing walls of the fin,
wherein the body region and the drain extension region are arranged one after another between the source region and the drain region.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming the gate structure on a top face of the fin.

### Claim 19 (depends on 17)

The method of claim 17, wherein the drain extension region is formed at least partly in the fin.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
forming a buried layer in a semiconductor substrate; and
forming a doped semiconductor layer on the buried layer.

### Claim 21 (depends on 17)

The method of claim 17, further comprising forming a shallow trench isolation on top of the fin adjoining the drain extension region.

### Claim 22 (depends on 17)

The method of claim 17, further comprising forming a deep body region of the second conductivity type below the fin.

### Claim 23 (depends on 17)

The method of claim 17, further comprising doping the body region by multiple masked ion implantations.

### Claim 24 (depends on 17)

The method of claim 17, wherein forming the source region and the drain region includes:
forming a first contact trench extending from the first side into the semiconductor body;
forming a second contact trench extending from the first side into the semiconductor body;
adjusting a height of the fin between 0.5 μm and 20 μm;
doping walls and a bottom side of each one of the first and second contact trenches;
filling the first contact trench and the second contact trench with a conductive material.

### Claim 25 (depends on 17)

The method of claim 17, wherein forming the drain extension region, the fin, and the body region includes:
forming the drain extension region on a semiconductor substrate by epitaxy; and
forming the body region by implanting dopants in at least a part of the fin.