# US 2014/0151803 A1 · Inducing Channel Stress in Semiconductor-on-Insulator Devices by Base Substrate Oxidation

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151803 A1
- Document ID: US20140151803A1
- Status: Published application
- Kind: A1
- Application number: 13/692,069
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: International Business Machines Corporation
- Inventors: Kangguo Cheng; Bruce B. Doris; Balasubramanian S. Haran; Ali Khakifirooz; Pranita Kerber
- Web page: https://patentgrep.com/patent/US20140151803A1

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 86/01: Manufacture or treatment
- H10W 10/0121: {in regions recessed from the surface, e.g. in trenches or grooves}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.

## Claims

### Claim 1

A method of forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer, the method comprising:
etching the SOI layer and the BOX layer to form a first and a second isolation recess region, wherein a portion of the SOI layer between the first and the second isolation recess region defines a channel region in the SOI layer; and
oxidizing a portion of the base substrate layer below the first and the second to form a first and a second oxide region, wherein the first and the second oxide region apply compressive strain to the channel region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the SOI layer has a thickness of approximately 3 nm to approximately 20 nm and the BOX layer has a thickness of approximately 10 nm to approximately 80 nm.

### Claim 3 (depends on 1)

The method of claim 1, further comprising protecting the channel region from oxidation prior to oxidizing the portion of the base substrate layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein protecting the channel region from oxidation comprises forming spacers on sidewalls of the first isolation recess region and on sidewalls of the second isolation recess region.

### Claim 5 (depends on 3)

The method of claim 3, wherein protecting the channel region from oxidation comprises implanting an oxidation-inhibiting species into a first end of the channel region adjacent to the first isolation recess region and a second end of the channel region adjacent to the second isolation recess region.

### Claim 6 (depends on 1)

The method of claim 1, wherein oxidizing the portion of the base substrate layer comprises a thermal oxidation process.

### Claim 7 (depends on 6)

The method of claim 6, wherein the thermal oxidation process comprises a Local Oxidation of Silicon (LOCOS) process.

### Claim 8 (depends on 1)

The method of claim 1, further comprising deepening the first isolation recess region into the base substrate and deepening the second isolation recess region into the base substrate prior to oxidizing a portion of the base substrate layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming a first isolation region above the first oxide region, wherein a top surface of the first isolation region is coplanar with or above a bottom surface of the pad nitride layer; and
forming a second isolation region above the second oxide region, wherein a top surface of the first isolation region is coplanar with or above a bottom surface of the pad nitride layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming a first isolation region above the first oxide region and forming a second isolation region above the second oxide region comprises filling the first isolation recess region and the second isolation recess region with an insulating material.

### Claim 11

A strained semiconductor-on-insulator (SOI) substrate comprising:
a buried insulator (BOX) layer above a base substrate layer;
a strained semiconductor channel above the BOX layer;
a first oxide region and a second oxide region partially within the base substrate layer, wherein the first oxide region and the second oxide region are adjacent to opposing ends of the strained semiconductor channel layer;
a first isolation structure above the first oxide region; and
a second isolation structure above the second oxide region.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the strained semiconductor channel has a thickness of approximately 3 nm to approximately 20 nm and the BOX layer has a thickness of approximately 10 nm to approximately 80 nm.

### Claim 13 (depends on 11)

The structure of claim 11, further comprising a spacer adjacent to the first end of the strained semiconductor channel and a spacer adjacent to the second end of the strained semiconductor channel.

### Claim 14 (depends on 11)

The structure of claim 11, further comprising oxidation inhibiting regions in the first end of the strained semiconductor channel and in the second end of the strained semiconductor channel.

### Claim 15

A semiconductor device comprising:
a semiconductor-on-insulator (SOI) substrate comprising a buried insulator (BOX) layer above a base substrate layer, a SOI layer above the BOX layer;
a first and a second field effect transistor (FET) on the SOI layer, wherein the first and second FETs comprise pFET devices; and
a first isolation structure between the first FET and the second FET including an oxide region partially within the base substrate and an insulating region above the oxide region, wherein the oxide region applies compressive strain to the SOI layer below the first FET and the second FET.

### Claim 16 (depends on 15)

The structure of claim 15 wherein the SOI has a thickness of approximately 3 nm to approximately 20 nm and the BOX layer has a thickness of approximately 10 nm to approximately 80 nm.

### Claim 17 (depends on 15)

The structure of claim 15, further comprising spacers between the first isolation structure and the SOI layer.

### Claim 18 (depends on 15)

The structure of claim 15, further comprising oxidation inhibiting regions in the SOI layer adjacent to the isolation structure.

### Claim 19 (depends on 15)

The structure of claim 15, further comprising:
a third FET on the SOI layer comprising a nFET device;
a fourth FET on the SOI layer comprising a pFET device or an nFET device; and
a second isolation structure between the third FET and the fourth FET, wherein the second isolation structure does not apply compressive strain to the SOI layer between the third FET and the fourth FET.

### Claim 20 (depends on 19)

The structure of claim 19, wherein the second isolation structure comprises a shallow trench isolation structure.