# US 2014/0151799 A1 · Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof

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- Number: US 2014/0151799 A1
- Document ID: US20140151799A1
- Status: Published application
- Kind: A1
- Application number: 14/173,571
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2012-07-22
- Assignees: Richtek Technology Corporation, R.O.C.
- Inventors: Tsung-Yi Huang; Chien-Hao Huang
- Web page: https://patentgrep.com/patent/US20140151799A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/836: {comprising EDMOS}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

## Claims

### Claim 1

A double diffused drain metal oxide semiconductor (DDDMOS) device formed in a first conductive type substrate, wherein a low voltage device is also formed in the substrate, the DDDMOS device comprising:
a second conductive type first well, which is formed in the substrate by a process step which also forms a second well in the low voltage device;
a first gate, which is formed on the substrate, wherein the first gate has a first side and a second side opposite to each other with respect to a channel direction, wherein part of the first well is located below part of the first gate including the first side;
a first conductive type diffusion region, which is formed in the substrate by a process step which also forms a lightly doped drain in the low voltage device, wherein at least part of the diffusion region is located outside the second side of the first gate; and
a first source and a first drain of first conductive type, which are formed in the substrate outside the first side and the second side of the first gate respectively, wherein the first drain and the first gate are separated by part of the diffusion region, and the first source is located in the first well.

### Claim 2 (depends on 1)

The DDDMOS device of claim 1, wherein the substrate includes a non-epitaxial substrate, and the DDDMOS device further includes a second conductive type first deep well, which is formed in the substrate by a process step which also forms a second deep well in the low voltage device, wherein the first well, the diffusion region, the first source and the first drain are located in the first deep well.

### Claim 3 (depends on 1)

The DDDMOS device of claim 1, wherein the substrate includes an epitaxial layer, wherein the first well, the diffusion region, the first source, and the first drain are located in the epitaxial layer, and the first gate is on the epitaxial layer.

### Claim 4 (depends on 3)

The DDDMOS device of claim 3, further comprising a second conductive type buried layer, which is formed in the substrate beneath the epitaxial layer.

### Claim 5 (depends on 1)

The DDDMOS device of claim 1, wherein the low voltage device further includes a second gate, a second source, and a second drain, wherein the first gate, the first source, and the first drain are formed by process steps which also form the second gate, the second source, and the second drain respectively.

### Claim 6 (depends on 1)

The DDDMOS device of claim 1, further comprising at least one field oxide region in the substrate, by which a device region of the DDDMOS device is defined, wherein an isolation region is formed below the one field oxide region by a process step which also forms the first well, wherein the one field oxide region is located relatively nearer to the first drain.

### Claim at position 7

7-12. (canceled)