# US 2014/0151798 A1 · Semiconductor Device and Method of Manufacturing a Semiconductor Device

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- Number: US 2014/0151798 A1
- Document ID: US20140151798A1
- Status: Published application
- Kind: A1
- Application number: 13/692,059
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Andreas Meiser; Till Schloesser
- Web page: https://patentgrep.com/patent/US20140151798A1

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/0287: {using recessing of the source electrodes}
- H10D 30/0289: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/658: {having trench gate electrodes}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 62/152: {Source regions of DMOS transistors}
- H10D 62/156: {Drain regions of DMOS transistors}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.

## Claims

### Claim 1

A semiconductor device comprising a transistor formed in a semiconductor substrate having a first main surface, the transistor comprising:
a source region;
a drain region;
a channel region;
a drift zone;
a gate electrode adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the channel region patterned into a first ridge extending along the first direction by adjacent first trenches in the semiconductor substrate; and
a first field plate being arranged adjacent to the drift zone.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode is disposed at at least two sides of the ridge.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the ridge comprises a top side and two sidewalls.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein a conductive inversion layer is formed along at least one of the sidewalls when the semiconductor device is operated in an on state.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein a portion of the drift zone is patterned into a second ridge extending along the first direction by adjacent second trenches in the semiconductor substrate.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein portions of the first field plate are disposed at at least two sides of the second ridge.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the second ridge has a width different from a width of the first ridge.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode and the first field plate are isolated from each other.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, further comprising a second field plate, the second field plate arranged adjacent to the first main surface along the first direction between the first field plate and the drain region.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the second field plate is coupled to an electrical potential and the first field plate is coupled to an electrical potential that is different than the electrical potential coupled to the second plate.

### Claim 11 (depends on 5)

The semiconductor device according to claim 5, wherein a further portion of the drift zone is patterned into a third ridge extending along the first direction by adjacent third trenches in the semiconductor substrate, the semiconductor device further comprising a second field plate, the second field plate arranged adjacent to the third ridge between the first field plate and the drain region.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the third ridge has a width that is different from a width of the second ridge.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the first ridge d is: d≦2×ld, wherein ld denotes a length of a depletion zone formed at an interface between the first ridge and the gate electrode.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, wherein the source and the drain region are disposed within the semiconductor substrate and extend approximately to a depth to which the gate electrode extends from the first main surface in a depth direction of the semiconductor substrate.

### Claim 15

A semiconductor device formed in a semiconductor substrate comprising a first main surface and a transistor, the transistor comprising:
a source region;
a drain region;
a channel region;
a drift zone; and
a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the channel region patterned into a first ridge extending in the first direction by adjacent first trenches in the semiconductor substrate, the first ridge having a first width d1 with:
d1≦2×ld,
wherein ld denotes a length of a depletion zone formed at an interface between the first ridge and a gate dielectric, the gate dielectric disposed between the first ridge and the gate electrode.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the following equation holds:
s1/d1>2.0, wherein s1 denotes the length of the ridge measured along a first direction.

### Claim 17 (depends on 15)

The semiconductor device according to claim 15, further comprising a field plate disposed adjacent to the drift zone.

### Claim 18 (depends on 15)

The semiconductor device according to claim 15, wherein the drift zone is a doped portion having a doping concentration that increases with increasing distance to the source region.

### Claim 19 (depends on 15)

The semiconductor device according to claim 15, further comprising a gate dielectric layer disposed between the gate electrode and the ridge and a field oxide disposed between the field plate and the drift zone, wherein a thickness of the field oxide layer increases with increasing distance from the source region.

### Claim 20 (depends on 15)

The semiconductor device according to claim 15, wherein the gate electrode is disposed at at least two sides of the first ridge.

### Claim 21

A method of manufacturing a semiconductor device in a semiconductor substrate, the semiconductor substrate comprising a first main surface and a transistor, wherein forming the transistor comprises:
forming a source region, a drain region, a channel region, a drift zone and a gate electrode adjacent to the channel region, wherein the channel region and the drift zone are formed so as to be disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, wherein forming the channel region comprises forming a first ridge in the semiconductor substrate, the first ridge extending along the first direction, the first ridge having a first width d1 with: d1≦2×ld, wherein ld denotes a length of a depletion zone formed at an interface between the first ridge and a gate dielectric, the gate dielectric disposed between the first ridge and the gate electrode.

### Claim 22 (depends on 21)

The method according to claim 21, wherein forming the first ridge and forming the gate electrode is accomplished by a method comprising forming gate trenches in the semiconductor substrate and forming a conductive layer so as to fill adjacent trenches.

### Claim 23 (depends on 21)

The method according to claim 21, further comprising forming a field plate adjacent to the drift zone.

### Claim 24 (depends on 23)

The method according to claim 23, wherein forming a field plate comprises forming field plate trenches in the semiconductor substrate and forming a conductive layer so as to fill the field plate trenches.

### Claim 25 (depends on 23)

The method according to claim 23, wherein forming the gate electrode comprises forming gate trenches in the semiconductor substrate and forming a field plate comprises forming field plate trenches in the semiconductor substrate, wherein the gate trenches and the field plate trenches are formed so that a pitch between adjacent gate trenches is different from a pitch between adjacent field plate trenches, forming the gate trenches and forming the field plate trenches being performed by a joint etching process.