# US 2014/0151794 A1 · Semiconductor device including a redistribution layer and metallic pillars coupled thereto

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- Number: US 2014/0151794 A1
- Document ID: US20140151794A1
- Status: Published application
- Kind: A1
- Application number: 14/091,626
- Filed: 2013-11-27
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Enpirion, Inc.
- Applicants: Enpirion, Inc.
- Inventors: Ashraf W. Lotfi; Jeffrey Demski; Anatoly Feygenson; Douglas Dean Lopata; Jay Norton; John D. Weld
- Web page: https://patentgrep.com/patent/US20140151794A1

## CPC

- H10D 89/10: Integrated device layouts
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 40/10: Arrangements for heating
- H10W 70/40: Leadframes
- H10W 70/475: {Capacitors in combination with leadframes}
- H10W 72/073: {of die-attach connectors}
- H10W 90/00: Package configurations
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10W 20/0698: {Local interconnections}
- H10W 20/071: {of dielectric parts thereof}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells forming an LDMOS device;
a redistribution layer electrically coupled to said plurality of LDMOS cells; and
a plurality of metallic pillars distributed over and electrically coupled to said redistribution layer.

### Claim 2 (depends on 1)

The semiconductor device as recited in claim 1, further comprising a plurality of gate drivers electrically coupled to said redistribution layer and to gates of said plurality of LDMOS cells.

### Claim 3 (depends on 1)

The semiconductor device as recited in claim 1, further comprising a conductive patterned leadframe electrically coupled to said redistribution layer by said plurality of metallic pillars.

### Claim 4 (depends on 3)

The semiconductor device as recited in claim 3, wherein said semiconductor device is potted with an encapulant.

### Claim 5 (depends on 4)

The semiconductor device as recited in claim 4, wherein portions of said conductive patterned leadframe are exposed to serve as external contacts for said semiconductor device.

### Claim 6 (depends on 5)

The semiconductor device as recited in claim 5, wherein ones of said external contacts are configured to be coupled to a printed circuit board.

### Claim 7 (depends on 6)

The semiconductor device as recited in claim 6, wherein ones of said external contacts are configured to be coupled to a plurality of decoupling devices on said printed circuit board.

### Claim 8 (depends on 6)

The semiconductor device as recited in claim 6, wherein ones of said external contacts are configured to be coupled to a plurality of decoupling devices through vias on an opposing surface of said printed circuit board.

### Claim 9 (depends on 8)

The semiconductor device as recited in claim 8, wherein said at least one of said plurality of decoupling devices is located under said semiconductor die.

### Claim 10 (depends on 5)

The semiconductor device as recited in claim 5, wherein ones of said external contacts are coupled to a plurality of gate drivers electrically coupled to said redistribution layer and to gates of said plurality of LDMOS cells.

### Claim 11 (depends on 5)

The semiconductor device as recited in claim 5, wherein ones of said external contacts are coupled to drains or sources of said plurality of LDMOS cells through said redistribution layer.

### Claim 12 (depends on 1)

The semiconductor device as recited in claim 1, wherein said plurality of metallic pillars comprises copper.

### Claim 13 (depends on 1)

The semiconductor device as recited in claim 1, wherein said plurality of metallic pillars is formed as electroplated columns.

### Claim 14 (depends on 1)

The semiconductor device as recited in claim 1, further comprising a metallic layer formed below said redistribution layer including a plurality of alternating source and drain metallic strips formed above a substrate of said semiconductor die and parallel to and forming an electrical contact with respective ones of a plurality of source and drain regions of said LDMOS device.

### Claim 15

A method of forming a semiconductor device, comprising:
forming a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells of an LDMOS device in a semiconductor die;
coupling a redistribution layer to said plurality of LDMOS cells; and
distributing over and coupling a plurality of metallic pillars to said redistribution layer.

### Claim 16 (depends on 15)

The method as recited in claim 15, further comprising coupling a plurality of gate drivers to said redistribution layer and to gates of said plurality of LDMOS cells.

### Claim 17 (depends on 15)

The method as recited in claim 15, further comprising:
coupling a conductive patterned leadframe to said redistribution layer by said plurality of metallic pillars; and
potting said semiconductor device with an encapulant, wherein portions of said conductive patterned leadframe are exposed to serve as external contacts for said semiconductor device.

### Claim 18 (depends on 17)

The method as recited in claim 17, wherein ones of said external contacts are coupled to a plurality of gate drivers coupled to said redistribution layer and to gates of said plurality of LDMOS cells.

### Claim 19 (depends on 17)

The method as recited in claim 17, wherein ones of said external contacts are coupled to drains or sources of said plurality of LDMOS cells through said redistribution layer.

### Claim 20 (depends on 15)

The method as recited in claim 15, further comprising forming a metallic layer below said redistribution layer including a plurality of alternating source and drain metallic strips formed above a substrate of said semiconductor die and parallel to and forming an electrical contact with respective ones of a plurality of source and drain regions of said LDMOS device.