# US 2014/0151790 A1 · Approach to integrate schottky in mosfet

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- Number: US 2014/0151790 A1
- Document ID: US20140151790A1
- Status: Published application
- Kind: A1
- Application number: 13/873,017
- Filed: 2013-04-29
- Published: 2014-06-05
- Earliest claimed: 2011-04-04
- Assignees: Alpha and Omega Semiconductor Incorporated
- Inventors: Sik Lui; Yi Su; Daniel Ng; Anup Bhalla
- Web page: https://patentgrep.com/patent/US20140151790A1

## CPC

- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D 8/605: {of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

## Claims

### Claim 1

A device, comprising:
a) a plurality of trenches formed into a semiconductor substrate and extending into the substrate forming a plurality of mesas there between, each trench being substantially filled with a conductive material that is separated from the trench walls by a thin layer of dielectric material to form a gate region of one or more field effect transistors;
b) at least two contact trenches formed in each mesa, each contact trench extending along a portion of depth of a doped body region of a first conductivity type opposite that of the substrate formed inside each mesa, whereby at least two contact trenches are separated by an exposed portion of the substrate;
c) a pair of doped source regions of a second conductivity type formed adjacent to and on opposite sides of each contact trench inside the doped body region; and
d) a Schottky diode comprising Schottky barrier metal formed over the exposed portion of the substrate, the Schottky barrier metal forming a Schottky junction at an interface between the Schottky barrier metal and an exposed surface of the exposed portion of the substrate separating the two contact trenches.

### Claim 2 (depends on 1)

The device of claim 1, wherein the doped body regions are separated by the exposed portion of the substrate.

### Claim 3 (depends on 1)

The device of claim 1, wherein the substrate includes an epitaxial layer formed thereon.

### Claim 4 (depends on 2, 3)

The device of claims 2 and 3, wherein the portion of the substrate separating the two doped body regions is the epitaxial layer.

### Claim 5 (depends on 1)

The device of claim 1, wherein the Schottky barrier metal is formed within each contact trench and along each exposed vertical sidewall at the ends of the contact trench.

### Claim 6 (depends on 1)

The device of claim 1, wherein each contact trench has an end that abuts the exposed portion of the substrate.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first conductivity type is p type.

### Claim 8 (depends on 1)

The device of claim 1, wherein the second conductivity type is n type.

### Claim 9 (depends on 1)

The device of claim 1, wherein the Schottky diode and one or more MOSFET devices are integrated into different adjacent mesas.

### Claim 10

A method for forming an integrated structure combining one or more field effect transistors and a Schottky diode, the method comprising:
a) forming a plurality of trenches formed into a semiconductor substrate and extending into the substrate thereby forming a plurality of mesas there between, each trench being substantially filled with a conductive material that is separated from the trench walls by a thin layer of dielectric material to form a gate region of one or more field effect transistors;
b) forming at least two contact trenches in each mesa, each contact trench extending along a portion of depth of a doped body region of a first conductivity type opposite that of the substrate formed inside each mesa, whereby at least two contact trenches are separated by an exposed portion of the substrate;
c) forming a pair of doped source regions of a second conductivity type formed adjacent to and on opposite sides of each contact trench inside the doped body region; and
d) forming a Schottky diode comprising Schottky barrier metal formed over the exposed portion of the substrate, the Schottky barrier metal forming a Schottky junction at an interface between the Schottky barrier metal and an exposed surface of the exposed portion of the substrate separating the two contact trenches.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming a doped shielding region of the first conductivity type inside each doped body region, the doped shielding region extending along an entire depth of the doped body region and into a portion of the exposed vertical sidewall of the exposed portion of the substrate composition separating the two doped body regions.

### Claim 12 (depends on 11)

The method of claim 11, wherein the doped shielding region is heavily doped.

### Claim 13 (depends on 11)

The method of claim 11, wherein the substrate composition is a substrate.

### Claim 14 (depends on 11)

The method of claim 11, wherein the substrate composition is a substrate with an epitaxial layer formed thereon.

### Claim 15 (depends on 14)

The method of claim 14, wherein the portion of the substrate composition separating the two doped body regions is the epitaxial layer.

### Claim 16 (depends on 11)

The method of claim 11, wherein the doped shielding region surrounds all bottom corners of the contact trench formed by the doped body region and extends into a bottom portion of the exposed vertical sidewall of the substrate.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming an additional doped shielding region of the first conductivity type inside a top surface of the exposed portion of the substrate composition separating the two doped body regions.

### Claim 18 (depends on 11)

The method of claim 11, wherein the doped shielding region extends along an entire width or length of sidewalls of the contact trench formed by the body regions, the doped shielding region also being formed within a portion of the exposed vertical sidewall of the substrate composition, the doped shielding region extending along an entire width or length of the exposed vertical sidewall.

### Claim 19 (depends on 11)

The method of claim 11, wherein the first conductivity type is p type.

### Claim 20 (depends on 11)

The method of claim 11, wherein the second conductivity type is n type.

### Claim 21 (depends on 11)

The method of claim 11, wherein the Schottky diode and one or more MOSFET devices are integrated into different adjacent mesas.