# US 2014/0151785 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151785 A1 - Document ID: US20140151785A1 - Status: Published application - Kind: A1 - Application number: 14/238,915 - Filed: 2012-09-04 - Published: 2014-06-05 - Earliest claimed: 2011-09-27 - Assignees: Denso Corporation - Inventors: Nozomu Akagi; Yuma Kagata; Makoto Kuwahara - Web page: https://patentgrep.com/patent/US20140151785A1 ## CPC - H10D 64/115: {Resistive field plates, e.g. semi-insulating field plates} - H10D 30/665: {having edge termination structures} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 64/112: {comprising multiple field plate segments} - H10D 84/141: {VDMOS having built-in components} - H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes} - H10D 62/157: {Impurity concentrations or distributions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The element electrodes of a semiconductor element are disposed in a cell region, while an outermost peripheral electrode electrically connected to a semiconductor substrate is disposed in a peripheral region. In the peripheral region, a second-conductivity-type layer is disposed above a super-junction structure. A potential division region is disposed above the second-conductivity-type layer to electrically connect the element electrodes and the outermost peripheral electrode and also divide the voltage between the element electrodes and the outermost peripheral electrode into a plurality of stages. A part of the potential division region overlaps the peripheral region when viewed from the thickness direction of the semiconductor substrate. ## Claims ### Claim 1 A semiconductor device including a cell region and a peripheral region surrounding the cell region, the semiconductor device comprising: a semiconductor substrate including a first-conductivity-type layer, and first-conductivity-type column regions and second-conductivity-type column regions formed above the first-conductivity-type layer and serving as a drift region, the first-conductivity-type column regions and the second-conductivity-type column regions forming a super-junction structure, a part of the semiconductor substrate being included in the cell region and other part of the semiconductor substrate being included in the peripheral region; a semiconductor element disposed in the cell region; element electrodes of the semiconductor element disposed in the cell region; an outermost peripheral electrode electrically connected to the semiconductor substrate in the peripheral region; a second-conductivity-type layer formed above the super-junction structure in the peripheral region; and a potential division region formed above the second-conductivity-type layer to electrically connect the element electrodes to the outermost peripheral electrode and also divide a voltage between the element electrodes and the outermost peripheral electrode into a plurality of stages, a part of the potential division region overlapping the peripheral region when viewed from a thickness direction of the semiconductor substrate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the potential division region divides the voltage between the element electrodes and the outermost peripheral electrode from the element electrode side toward the outermost peripheral electrode side such that a potential distribution in the super-junction structure has equal intervals in a planar direction of the first-conductivity-type layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein, in the planar direction of the first-conductivity-type layer, a length of the potential division region from an end portion located on the cell region side to an end portion located on the outermost peripheral electrode side is greater than a depth from a surface of the second-conductivity-type layer to the first-conductivity-type layer. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the outermost peripheral electrode overlaps the super-junction structure when viewed from the thickness direction of the semiconductor substrate. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the peripheral region further includes a charge balance change region in which a balance between impurity concentrations in the first-conductivity-type column regions and the second-conductivity-type column regions, which form the super-junction structure, continuously changes toward a side opposite to the cell region. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the charge balance change region is adjacent to the cell region. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein the first-conductivity-type column regions and the second-conductivity-type column regions, which form the super-junction structure, are repeatedly arranged in a repetition direction all over the cell region and the peripheral region, and wherein, in the peripheral region, widths of the second-conductivity-type column regions in a direction perpendicular to the repetition direction in the planar direction of the first-conductivity-type layer continuously decrease toward end portions of the second-conductivity-type column regions to continuously change the balance between the impurity concentrations in the charge balance change region. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein, in the cell region and the peripheral region, the first-conductivity-type column regions and the second-conductivity-type column regions are repeated with a constant pitch, and wherein, in the peripheral region, the widths of the second-conductivity-type column regions continuously decrease toward the side opposite to the cell region to continuously change the balance between the impurity concentrations in the charge balance change region. ### Claim 9 (depends on 5) The semiconductor device according to claim 5, wherein, in the peripheral region, the first-conductivity-type column regions and the second-conductivity-type column regions, which form the super-junction structure, are laid out in a ring shape surrounding the cell region, while the first-conductivity-type column regions and the second-conductivity-type column regions are repeatedly arranged in a repetition direction toward the side opposite to the cell region, and wherein, in the peripheral region, widths of the first-conductivity-type column regions increase with increasing distance from the cell region in the repetition direction to continuously change the balance between the impurity concentrations in the charge balance change region. ### Claim 10 (depends on 5) The semiconductor device according to claim 5, wherein the super-junction structure is configured such that the second-conductivity-type column regions are scattered in a dotted shape in the first-conductivity-type column region, and wherein a ratio of the second-conductivity-type column regions formed in the peripheral region is lower than a ratio of the second-conductivity-type column regions formed in the cell region and decreases toward an outer peripheral direction of the cell region. ### Claim 11 (depends on 5) The semiconductor device according to claim 5, wherein the super-junction structure is configured such that, in the cell region, the first-conductivity-type column regions and the second-conductivity-type column regions are repeatedly and alternately formed using a direction parallel with the planar direction of the first-conductivity-type layer as a column longitudinal direction and using a direction perpendicular to the longitudinal direction as a column repetition direction while, in the peripheral region, the second-conductivity-type column regions are formed in a multi-round frame shape surrounding a periphery of the cell region, and wherein, in the peripheral region, intervals of the second-conductivity-type column regions configured in the multi-round frame shape increase toward an outer peripheral direction of the cell region. ### Claim 12 A semiconductor device including a cell region in which a semiconductor element is formed, and a peripheral region surrounding the cell region, the semiconductor device comprising: a semiconductor substrate including a first-conductivity-type layer, and first-conductivity-type column regions and second-conductivity-type column regions formed above the first-conductivity-type layer and serving as a drift region, the first-conductivity-type column regions and the second-conductivity-type column regions forming a super-junction structure, a part of the semiconductor substrate being included in the cell region and other part of the semiconductor substrate being included in the peripheral region, a first-conductivity-type charge amount and a second-conductivity-type charge amount in the super-junction structure being set equal in the cell region, the semiconductor substrate further including a charge balance change region in the peripheral region, wherein, in the charge balance change region, the first-conductivity-type charge amount in the super-junction structure is gradually increased to be larger than the second-conductivity-type charge amount toward an outer peripheral direction of the cell region. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the super-junction structure is configured such that the first-conductivity-type column regions and the second-conductivity-type column regions are repeatedly and alternately formed using a direction parallel with a planar direction of the first-conductivity-type layer as a column longitudinal direction and using a direction perpendicular to the column longitudinal direction as a column repetition direction, and wherein each of the second-conductivity-type column regions has a front end portion in the column longitudinal direction, and the front end portion is formed in a taper shape having a gradually reduced width such that a boundary surface with the first-conductivity-type column region becomes a taper shape inclined with respect to the column repetition direction. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein, in the super-junction structure, dimensions of the second-conductivity-type column regions in the column repetition direction are equal in the cell region and the peripheral region, wherein column pitches, which are repetition units of the first-conductivity-type column regions and the second-conductivity-type column regions, are equal in the cell region and, wherein the column pitches are increased in the peripheral direction toward the outer peripheral direction of the cell region to be larger than the column pitches in the cell region. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein, in the super-junction structure, the second-conductivity-type column regions in the peripheral region have dimensions in the column repetition direction which are gradually reduced with distance from the cell region toward the outer peripheral direction, and wherein column pitches, which are repetition units of the first-conductivity-type column regions and the second-conductivity-type column regions, are constant in the cell region and the peripheral region. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, wherein depths of the second-conductivity-type column regions decrease with distance from the cell region toward an outer periphery. ### Claim 17 (depends on 12) The semiconductor device according to claim 12, wherein, in the peripheral region, first-conductivity-type impurity concentrations in the first-conductivity-type column regions increase with distance from the cell region toward an outer periphery. ### Claim 18 (depends on 12) The semiconductor device according to claim 12, wherein the super-junction structure is configured such that, in the cell region, the first-conductivity-type column regions and the second-conductivity-type column regions are repeatedly and alternately formed using a direction parallel with a planar direction of the first-conductivity-type layer as a column longitudinal direction and using a direction perpendicular to the column longitudinal direction as a column repetition direction while, in the peripheral region, the second-conductivity-type column regions are configured in a multi-round frame shape surrounding a periphery of the cell region, and wherein, in the peripheral region, intervals of the second-conductivity-type column regions configured in the multi-round frame shape are increased toward the outer peripheral direction of the cell region. ### Claim 19 (depends on 12) The semiconductor device according to claim 12, wherein the super-junction structure is configured such that the second-conductivity-type column regions are scattered in a dotted shape in the first-conductivity-type column region, and wherein a ratio of the first-conductivity-type column regions formed in the peripheral region is lower than a ratio of the first-conductivity-type column regions formed in the cell region and is reduced toward the outer peripheral direction of the cell region. ### Claim 20 (depends on 12) The semiconductor device according to claim 12, wherein the super-junction structure includes a charge balance change structure in which a relationship between the first-conductivity-type charge amount and the second-conductivity-type charge amount gradually changes also in a depth direction, and wherein when the repetition unit of the first-conductivity-type column regions and the second-conductivity-type column regions is the column pitch and an excess concentration N is given by the excess concentration N=(the second-conductivity-type charge amount−the first-conductivity-type charge amount)/the column pitch), a concentration change gradient dN/dx=(N1−N2)/x of the excess concentration in the charge balance change region toward the outer peripheral direction when N1 is the excess concentration at an innermost peripheral position in the charge balance change region, N2 is the excess concentration at an outermost peripheral position in the charge balance change region extending from the cell region toward the outer peripheral direction, and x is a distance from the innermost peripheral position to the outermost peripheral position in the charge balance change region and a concentration change gradient dN/dz=(N3−N4)/z of the excess concentration in the depth direction in the charge balance change structure when N3 is the excess concentration at a surface position in the cell region, N4 is the excess concentration at a deepest position in the cell region, and z is a distance from the surface position to the deepest position in the cell region to satisfy a relationship of dN/dx≦dN/dz. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, wherein the excess concentration N2 at the outer periphery of the peripheral region and the excess concentration N4 at the deepest position in the cell region satisfy a relationship of N2>N4.