# US 2014/0151784 A1 · Semiconductor memory device and method of manufacturing the same

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- Number: US 2014/0151784 A1
- Document ID: US20140151784A1
- Status: Published application
- Kind: A1
- Application number: 13/830,912
- Filed: 2013-03-14
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: SK hynix Inc.
- Applicants: SK Hynix Inc.
- Inventors: Sang Hyon KWAK
- Web page: https://patentgrep.com/patent/US20140151784A1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/0111: {to Group IV semiconductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a channel layer;
interlayer insulation layers surrounding the channel layer, wherein the interlayer insulation layers are stacked with a trench interposed therebetween;
a seed pattern formed on a surface of the trench; and
a metal layer formed on the seed pattern in the trench.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the metal layer covers an entire surface of the seed pattern.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein a width of each of the interlayer insulation layers is greater than a width of the seed pattern.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein a width of the metal layer is greater or less than a width of each of the interlayer insulation layers.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
barrier metal patterns formed between the seed pattern and the channel layer and between the seed pattern and the interlayer insulation layers.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the metal layer is formed of tungsten.

### Claim 7

A method of manufacturing a semiconductor memory device, the method comprising:
forming interlayer insulation layers surrounding a channel layer, wherein the interlayer insulation layers are stacked with a trench interposed therebetween;
forming a seed film on a surface of the trench and on surfaces of the interlayer insulation layers;
forming a sacrificial pattern in the trench;
forming a seed pattern in the trench by etching the seed film by using the sacrificial pattern as an etching barrier; and
growing a metal layer from the seed pattern in the trench.

### Claim 8 (depends on 7)

The method of claim 7, wherein the forming of the interlayer insulation layers surrounding the channel layer comprises:
alternately stacking the interlayer insulation layers and sacrificial layers;
forming the channel layer through the interlayer insulation layers and the sacrificial layers;
forming a slit through the interlayer insulation layers and the sacrificial layers to expose the sacrificial layers; and
forming the trench by removing the sacrificial layers.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
forming a barrier metal layer along a surface of the trench and along surfaces of the interlayer insulation layers before the forming of the seed film.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
forming a barrier metal pattern under the seed pattern by etching the barrier metal layer by using the sacrificial pattern as an etching barrier.

### Claim 11 (depends on 7)

The method of claim 7 wherein a width of the sacrificial pattern is less than a width of each of the interlayer insulation layers.

### Claim 12 (depends on 7)

The method of claim 7, wherein the metal layer is to cover an entire surface of the seed pattern.

### Claim 13 (depends on 7)

The method of claim 7, wherein a width of the metal layer is greater or less than a width of each of the interlayer insulation layers.

### Claim 14 (depends on 7)

The method of claim 7, wherein the forming the seed film comprises:
forming the seed film using a reducing gas.

### Claim 15 (depends on 14)

The method of claim 14, wherein the growing the metal layer comprises:
removing the reducing gas using a purge gas; and
substituting the seed pattern with the metal layer via a metal source gas.