# US 2014/0151782 A1 · Methods and Apparatus for Non-Volatile Memory Cells with Increased Programming Efficiency

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- Number: US 2014/0151782 A1
- Document ID: US20140151782A1
- Status: Published application
- Kind: A1
- Application number: 14/176,968
- Filed: 2014-02-10
- Published: 2014-06-05
- Earliest claimed: 2012-11-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yong-Shiuan Tsair; Wen-Ting Chu; Po-Wei Liu; Wen-Tuo Huang; Yu-Hsiang Yang; Chieh-Fei Chiu; Yu-Ling Hsu
- Web page: https://patentgrep.com/patent/US20140151782A1

## CPC

- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

## Claims

### Claim 1

An method comprising:
providing a substrate;
forming a floating gate over the substrate and a control gate over the floating gate, the floating gate having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate;
forming a first dielectric layer over a first sidewall and a second sidewall of the control gate, the first dielectric layer completely covering an upper surface of the second portion of the floating gate, the first dielectric layer being in direct contact with the control gate; and
forming a second dielectric layer over the first dielectric layer, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate, the first dielectric layer completely separating the second dielectric layer from the upper surface of the second portion of the floating gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first dielectric layer forms an L-shaped liner along the second side of the control gate.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming an erase gate extending over at least a portion of the floating gate.

### Claim 4 (depends on 3)

The method of claim 3, wherein the erase gate overlies at least 5 percent of the floating gate.

### Claim 5 (depends on 3)

The method of claim 3, wherein the erase gate overlies between 5 and 20 percent of the floating gate.

### Claim 6 (depends on 3)

The method of claim 3, wherein the erase gate overlies between 5 and 10 percent of the upper surface of the floating gate.

### Claim 7

A method comprising:
forming a floating gate layer over a semiconductor substrate and a control gate layer over the floating gate layer;
patterning the control gate layer, thereby forming a control gate having a first sidewall on a first side and a second sidewall on a second side;
forming a first dielectric layer over the first sidewall and the second sidewall of the control gate;
patterning the first dielectric layer along the first sidewall such that the first dielectric layer is discontinuous with the first dielectric layer along the second sidewall;
after the patterning the first dielectric layer, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall;
patterning the second dielectric layer along the first sidewall and the second sidewall, the second dielectric layer being in direct contact with the floating gate layer on the first side of the control gate; the first dielectric layer being interposed between the second dielectric layer and the floating gate layer on the second side of the control gate;
patterning the floating gate layer using the first dielectric layer and the second dielectric layer as a mask, thereby forming a floating gate;
removing the second dielectric layer along the first sidewall; and
forming an erase gate along the first sidewall, the erase gate overlying at least a portion of the floating gate.

### Claim 8 (depends on 7)

The method of claim 7, further comprising masking the second dielectric layer along the second sidewall prior to the removing the second dielectric layer along the first sidewall, such that the second dielectric layer along the second sidewall remains.

### Claim 9 (depends on 7)

The method of claim 7, after the patterning the floating gate, further comprising forming a third dielectric layer over the second dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, patterning the third dielectric layer, thereby exposing the semiconductor substrate in a common source region on a first side of the floating gate.

### Claim 11 (depends on 7)

The method of claim 7, wherein the forming the erase gate comprises forming a third dielectric layer over an exposed portion of the floating gate on the first side of the control gate, and forming the erase gate over the third dielectric layer.

### Claim 12 (depends on 7)

The method of claim 7, wherein the erase gate overlies at least 5 percent of the floating gate.

### Claim 13 (depends on 7)

The method of claim 7, wherein the erase gate overlies between 5 and 20 percent of the floating gate.

### Claim 14 (depends on 7)

The method of claim 7, wherein the erase gate overlies between 5 and 10 percent of the floating gate.

### Claim 15

An apparatus comprising:
a substrate;
a floating gate over the substrate;
a control gate over the floating gate, the floating gate having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate;
a first dielectric layer extending over a first sidewall and a second sidewall of the control gate, the first dielectric layer completely covering an upper surface of the second portion of the floating gate; and
a second dielectric layer over the first dielectric layer, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate, the first dielectric layer completely separating the second dielectric layer from the upper surface of the second portion of the floating gate.

### Claim 16 (depends on 15)

The apparatus of claim 15, further comprising an erase gate, the erase gate extending over the first portion of the floating gate.

### Claim 17 (depends on 16)

The apparatus of claim 16, further comprising a common source in the substrate below the erase gate.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers at least 5 percent of the upper surface of the floating gate.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers between 5 and 20 percent of the upper surface of the floating gate.

### Claim 20 (depends on 16)

The apparatus of claim 16, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers between 5 and 10 percent of the upper surface of the floating gate.