# US 2014/0151781 A1 · Process for fabricating a transistor comprising nanocrystals

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- Number: US 2014/0151781 A1
- Document ID: US20140151781A1
- Status: Published application
- Kind: A1
- Application number: 14/173,249
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2011-07-21
- Assignees: STMicroelectronics (Roesset) SAS
- Applicants: Stmicroelectronics (Rousset) SAS
- Inventors: PHILIPPE BOIVIN
- Web page: https://patentgrep.com/patent/US20140151781A1

## CPC

- H10D 30/0411: {of FETs having floating gates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/685: {from the channel}
- H10D 30/6893: {wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/30: characterised by the memory core region
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.

## Claims

### Claim at position 1

1-15. (canceled)

### Claim 16

A method for making a transistor comprising:
forming source and drain regions in a substrate;
forming a floating gate comprising a plurality of electrically conductive nanoparticles to accumulate electrical charge;
deoxidizing a part of the floating gate adjacent the source region to define a space; and
oxidizing the space to form an enlarged zone of an insulating layer adjacent the source region.

### Claim 17 (depends on 16)

The method according to claim 16 wherein deoxidizing comprises buffered oxide etching (BOE).

### Claim 18 (depends on 16)

The method according to claim 16 wherein the transistor is for an electrically programmable memory comprising a plurality of memory cells.

### Claim 19 (depends on 18)

The method according to claim 18 wherein the electrically programmable memory comprises a flash memory; and further comprising forming a self-aligned source by etching with a mask, the mask being used for deoxidizing on a source side between a number of gates of a number of transistors and the substrate.

### Claim 20

A method for making a transistor comprising:
forming source and drain regions in a substrate;
forming a floating gate comprising a plurality of electrically conductive nanoparticles to accumulate electrical charge;
removing a part of the floating gate adjacent the source region; and
forming an enlarged zone of an insulating layer adjacent the source region and in the removed part of the floating gate.

### Claim 21 (depends on 20)

The method according to claim 20 wherein deoxidizing comprises buffered oxide etching (BOE).

### Claim 22 (depends on 20)

The method according to claim 20 wherein the transistor is for an electrically programmable memory comprising a number of memory cells.

### Claim 23

A transistor comprising:
a substrate;
source and drain regions in said substrate;
a control gate above said substrate;
a first zone adjacent said drain region and between said substrate and said control gate, and comprising at least one floating gate including a plurality of electrically conductive nanoparticles configured to accumulate electrical charge; and
a second zone adjacent said source region and between said substrate and said control gate, and comprising a single insulating layer, the first zone having a thickness less than that of the second zone and configured to provide a vertical electric field that varies across the first and second zones during a transistor-programming operation.

### Claim 24 (depends on 23)

The transistor according to claim 23 wherein said second zone is devoid of conductive nanoparticles.

### Claim 25 (depends on 23)

The transistor according to claim 23 further comprising a channel region between said source region and said drain region; wherein said source region is partially under said control gate and defines a junction with said channel region between said drain region and said source region; and
wherein said second zone extends beyond the junction.

### Claim 26 (depends on 23)

The transistor according to claim 23 wherein said second zone has a length between 25% and 75% of a total gate length.

### Claim 27 (depends on 23)

The transistor according to claim 23 wherein said drain and source regions each comprises a region having a first conductivity type; and wherein said substrate has a second conductivity type opposite the first conductivity type.

### Claim 28 (depends on 25)

The transistor according to claim 25 wherein said channel region is configured to permit hot-carrier-injection.

### Claim 29

A non-volatile electrically programmable memory comprising:
a plurality of memory cells coupled to at least one word line and to at least one bit line, each memory cell comprising at least one transistor comprising
a substrate,
source and drain regions in said substrate,
a control gate above said substrate,
a first zone adjacent said drain region and between said substrate and said control gate, and comprising at least one floating gate including a plurality of electrically conductive nanoparticles configured to accumulate electrical charge, and
a second zone adjacent said source region and between said substrate and said control gate, and comprising a single insulating layer, the first zone having a thickness less than that of the second zone and configured to provide a vertical electric field that varies across the first and second zones during a transistor-programming operation for each memory cell.

### Claim 30 (depends on 29)

The non-volatile electrically programmable memory according to claim 29 where said plurality of memory cells comprises a plurality of flash memory cells.

### Claim 31 (depends on 29)

The non-volatile electrically programmable memory according to claim 29 where said plurality of memory cells comprises a plurality of Electrically Erasable Programmable Read-Only Memory (EEPROM) memory cells.

### Claim 32 (depends on 29)

The non-volatile electrically programmable memory according to claim 29 wherein said at least one transistor further comprises a channel region between said source region and said drain region; wherein said source region is partially under said control gate and defines a junction with said channel region between said drain region and said source region; and wherein said second zone extends beyond the junction.

### Claim 33 (depends on 29)

The non-volatile electrically programmable memory according to claim 29 wherein said second zone has a length between 25% and 75% of a total gate length.

### Claim 34 (depends on 29)

The non-volatile electrically programmable memory according to claim 29 wherein said drain and source regions each comprises a region having a first conductivity type;
and wherein said substrate has a second conductivity type opposite the first conductivity type.

### Claim 35

An electronic device comprising:
a device comprising a plurality of memory cells coupled to at least one word line and to at least one bit line, each memory cell comprising at least one transistor comprising
a substrate,
source and drain regions in said substrate,
a control gate above said substrate,
a first zone adjacent said drain region and between said substrate and said control gate, and comprising at least one floating gate including a plurality of electrically conductive nanoparticles configured to accumulate electrical charge, and
a second zone adjacent said source region and between said substrate and said control gate, and comprising a single insulating layer, the first zone having a thickness less than that of the second zone and configured to provide a vertical electric field that varies across the first and second zones during a transistor-programming operation for each memory cell.

### Claim 36 (depends on 35)

The electronic device according to claim 35 wherein said device comprises a smart card.

### Claim 37 (depends on 35)

The electronic device according to claim 35 where said plurality of memory cells comprises a plurality of flash memory cells.

### Claim 38 (depends on 35)

The electronic device according to claim 35 where said plurality of memory cells comprises a plurality of Electrically Erasable Programmable Read-Only Memory (EEPROM) memory cells.