# US 2014/0151780 A1 · Nonvolatile memory device and method of fabricating the same

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- Number: US 2014/0151780 A1
- Document ID: US20140151780A1
- Status: Published application
- Kind: A1
- Application number: 13/830,983
- Filed: 2013-03-14
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: SK hynix Inc.
- Applicants: SK Hynix Inc.
- Inventors: Sung-Kun PARK; Young-Jun KWON
- Web page: https://patentgrep.com/patent/US20140151780A1

## CPC

- H10B 41/10: characterised by the top-view layout
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 41/49: comprising different types of peripheral transistor
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A nonvolatile memory device includes a floating gate formed over a substrate, a select gate formed adjacent to the floating gate with a gap defined therebetween, spacers formed on sidewalls of the floating gate and the select gate and filling the gap, a first junction region formed in the substrate adjacent to the floating gate, and a second junction region formed in the substrate adjacent to the select gate.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a floating gate formed over a substrate;
a select gate formed adjacent to the floating gate with a gap defined therebetween;
spacers formed on sidewalls of the floating gate and the select gate and filling the gap;
a first junction region formed in a portion of the substrate adjacent to the floating gate; and
a second junction region formed in a portion of the substrate adjacent to the select gate.

### Claim 2 (depends on 1)

The nonvolatile memory device according to claim 1, further comprising:
a third junction region formed in a portion of the substrate under the gap.

### Claim 3 (depends on 2)

The nonvolatile memory device according to claim 2,
wherein the first junction region and the second junction region comprise first impurity regions and second impurity regions that have larger impurity doping concentrations than those of the first impurity regions, respectively, and
wherein the third junction region comprises an impurity region the same as the first impurity regions.

### Claim 4 (depends on 1)

The nonvolatile memory device according to claim 1, wherein the select gate has a sidewall that faces a sidewall of the floating gate.

### Claim 5 (depends on 1)

The nonvolatile memory device according to claim 1, wherein an upper surface of the floating gate and an upper surface of the select gate are positioned on a same plane.

### Claim 6 (depends on 1)

The nonvolatile memory device according to claim 1,
wherein the floating gate and the select gate comprise a polyslicon layer, and
wherein the spacers comprise a dielectric layer.

### Claim 7 (depends on 1)

The nonvolatile memory device according to claim 1, wherein the floating gate is coupled to the select gate in response to a voltage applied to the select gate.

### Claim 8 (depends on 1)

The nonvolatile memory device according to claim 1, wherein a coupling ratio between the select gate and the floating gate increases as a width of the gap decreases.

### Claim 9

A nonvolatile memory device comprising:
a plurality of active regions;
a plurality of gate lines crossing the plurality of active regions;
junction regions formed in the active regions between the gate lines; and
a first conductive line and a second conductive line respectively connected to one and the other junction regions when viewed on each of the plurality of gate lines,
wherein each of the plurality of gate lines comprises a plurality of floating gates, a select gate that is adjacent to the plurality of floating gates with gaps defined therebetween, and spacers that are formed on sidewalls of the floating gates and the select gate and fill the gaps.

### Claim 10 (depends on 9)

The nonvolatile memory device according to claim 9, wherein the plurality of floating gates are positioned over the plurality of active regions, and the select gate extends across the plurality of active regions.

### Claim 11 (depends on 9)

The nonvolatile memory device according to claim 9, wherein any one gate line and an adjacent gate line have shapes in which their floating gates or select gates face each other, or shapes in which the floating gates of the any one gate line and the select gate of the adjacent gate line face each other.

### Claim 12 (depends on 9)

The nonvolatile memory device according to claim 9, wherein a plurality of floating gates of any one gate line are coupled to the select gate in response to a voltage applied to a select gate of the any one gate line.

### Claim 13 (depends on 9)

The nonvolatile memory device according to claim 9, wherein coupling ratios between the select gate and the plurality of floating gates increase as a width of the gap decreases.