# US 2014/0151779 A1 · Semiconductor memory device and method of manufacturing the same

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- Number: US 2014/0151779 A1
- Document ID: US20140151779A1
- Status: Published application
- Kind: A1
- Application number: 13/780,927
- Filed: 2013-02-28
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: SK hynix Inc.
- Applicants: SK Hynix Inc.
- Inventors: Jung Il CHO; Jong Moo CHOI; Eun Joo JUNG
- Web page: https://patentgrep.com/patent/US20140151779A1

## CPC

- H10W 10/20: Air gaps
- H10B 41/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 64/01344: {in a nitrogen-containing ambient, e.g. N2O oxidation}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/665: {Porous materials}
- H10P 50/283: {by chemical means}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/021: {of air gaps}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a semiconductor substrate in which an active region and an isolation region are defined;
a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region;
a trench formed in the semiconductor substrate in the isolation region;
a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench; and
a control gate formed on the dielectric layer,
wherein the dielectric layer includes a first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the first nitride layer, the first oxide layer, the second nitride layer and the second oxide layer extend both in the active region and the isolation region.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, further comprising a liner insulating layer formed along a surface of the trench in the isolation region.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, further comprising a lower insulating layer formed under the air gap in the isolation region.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein a top surface of the lower insulating layer is lower than a top surface of the semiconductor substrate in the active region.

### Claim 6

A method of manufacturing a semiconductor memory device, the method comprising:
forming a tunnel insulating layer and a first conductive layer configured as a floating gate in an active region of a semiconductor substrate, and forming a trench in an isolation region of the semiconductor substrate;
filling the trench with a sacrificial layer having a top surface higher than a surface of the semiconductor substrate;
forming a first oxide layer along an entire surface of a resultant structure filled with the sacrificial layer;
forming an air gap in the isolation region by removing the sacrificial layer while maintaining the first oxide layer;
transforming a portion of the first oxide layer into a first nitride layer;
forming a second nitride layer and a second oxide layer over the first oxide layer; and
forming a second conductive layer configured as a control gate on the second oxide layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first oxide layer includes an ultra low temperature oxide layer.

### Claim 8 (depends on 6)

The method of claim 6, wherein the ultra low temperature oxide layer is formed using atomic layer deposition (ALD).

### Claim 9 (depends on 6)

The method of claim 6, wherein the ultra low temperature oxide layer is formed at a temperature ranging from approximately 50° C. to 100° C.

### Claim 10 (depends on 6)

The method of claim 6, wherein the first nitride layer is formed by transforming a lower portion of the first oxide layer into an SiON layer.

### Claim 11 (depends on 6)

The method of claim 6, wherein the first nitride layer is formed by performing plasma nitridation or annealing.

### Claim 12 (depends on 11)

The method of claim 11, wherein the plasma nitridation is performed under a nitrogen atmosphere at a temperature ranging from approximately 200° C. to 700° C.

### Claim 13 (depends on 11)

The method of claim 11, further comprising performing a stabilized process to improve quality of the first nitride layer after the first nitride layer is formed by performing the plasma nitridation.

### Claim 14 (depends on 13)

The method of claim 13, wherein the stabilizing process is performed by a plasma process under an oxygen atmosphere.

### Claim 15 (depends on 11)

The method of claim 11, wherein the annealing is performed at a temperature ranging from 600° C. to 1100° C.

### Claim 16 (depends on 11)

The method of claim 11, wherein the annealing is performed under an NO, N2 or N2O atmosphere.

### Claim 17 (depends on 6)

The method of claim 6, further comprising performing additional oxidation to improve quality of the first oxide layer after the transforming of the portion of the first oxide layer into the first nitride layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein O2 dry oxidation or O2 wet annealing is performed as the additional oxidation.

### Claim 19 (depends on 6)

The method of claim 6, further comprising forming a lower insulating layer in a lower part of the trench before the filling of the sacrificial layer.

### Claim 20 (depends on 6)

The method of claim 6, wherein the forming of the air gap in the isolation region is performed by generating oxygen, nitrogen or hydrogen plasma to remove the sacrificial layer.