# US 2014/0151777 A1 · Semiconductor Memory Devices and Methods of Fabricating the Same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151777 A1
- Document ID: US20140151777A1
- Status: Published application
- Kind: A1
- Application number: 14/096,195
- Filed: 2013-12-04
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jae-Hwang Sim; Jinhyun Shin; Jong-Min Lee
- Web page: https://patentgrep.com/patent/US20140151777A1

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a semiconductor substrate including a first trench that defines active regions in a first region and a second trench in a second region around the first region;
a gate electrode on the first region that crosses the active regions;
a data storing pattern that is between the gate electrode and the active regions;
a blocking insulating layer that is between the gate electrode and the data storing pattern and that extends over the first trench to define a first air gap in the first trench; and
an insulating pattern that is spaced apart from a bottom surface of the second trench to define a second air gap in the second trench;
wherein the first and second trenches have substantially a same depth,
wherein the first air gap includes a first vertical height and the second air gap includes a second vertical height, and
wherein the first vertical height is greater than the second vertical height.

### Claim 2 (depends on 1)

The device of claim 1,
wherein an uppermost position of the first air gap is located between a bottom surface of the data storing pattern and a top surface of the data storing pattern, and
wherein an uppermost position of the second air gap is located below a top surface of the semiconductor substrate.

### Claim 3 (depends on 1)

The device of claim 1,
wherein the blocking insulating layer conformally covers top and upper side surfaces of the data storing pattern, and
wherein a bottom surface of the blocking insulating layer on the first trench is located between a bottom surface of the data storing pattern and the top surface of the data storing pattern.

### Claim 4 (depends on 1)

The device of claim 1, wherein a thickness of the blocking insulating layer is smaller on the first trench than on a top surface of the data storing pattern.

### Claim 5 (depends on 1)

The device of claim 1, wherein the insulating pattern comprises:
a top surface that is positioned on a top surface of the semiconductor substrate; and
a rounded bottom surface that is positioned below the top surface of the semiconductor substrate.

### Claim 6 (depends on 1)

The device of claim 1, further comprising a contact plug that is adjacent the second trench in the second region and connected to the semiconductor substrate.

### Claim 7 (depends on 1)

The device of claim 1, wherein the semiconductor substrate has a first conductivity type and comprises:
a well region formed in the semiconductor substrate to have a second conductivity type; and
a pocket well region formed in the well region to have the first conductivity type, and
wherein the first trench is formed at a central portion of the pocket well region and the second trench is formed at an edge portion of the a pocket well region.

### Claim 8 (depends on 7)

The device of claim 7, further comprising:
a well pick-up region locally formed in the pocket well region to have an impurity concentration higher than that of the pocket well region and to have the first conductivity type; and
a well contact plug that is adjacent the second trench in the second region and connected to the semiconductor substrate.

### Claim 9 (depends on 1)

The device of claim 1, wherein the data storing pattern comprises a tunnel insulating layer and a floating gate electrode that are sequentially stacked on the semiconductor substrate.

### Claim 10 (depends on 1)

The device of claim 1, wherein the data storing pattern comprises a charge tunneling layer, a charge trap insulating layer, and a charge blocking layer that are sequentially stacked on the semiconductor substrate.

### Claim 11 (depends on 1)

The device of claim 1, wherein the semiconductor substrate comprises a third trench formed on the second region to have a bottom surface that is lower than that of the second trench,
the device further comprising a peripheral insulating pattern spaced apart from the bottom surface of the third trench to define a third air gap in the third trench.

### Claim 12 (depends on 11)

The device of claim 11, wherein an uppermost position of the third air gap is located below an uppermost position of the first air gap, and a lowermost position of the third air gap is located below a lowermost position of the first air gap.

### Claim 13 (depends on 11)

The device of claim 11, wherein the third air gap includes a third vertical height that is greater than the second vertical height.

### Claim 14

A semiconductor memory device, comprising:
a semiconductor substrate comprising a plurality of first active regions extending side-by-side along a first direction and a second active region extending along a second direction that is substantially perpendicular to the first direction to cross the first active regions, the first and second active regions being defined by a trench;
a common source that is in the second active region and that extends along the second direction;
a plurality of drains in the plurality of first active regions, respectively;
gate lines that are between the common source and the plurality of drains and that cross the first active regions;
data storing patterns interposed between the gate lines and the first active regions; and
an air gap that is between a bottom surface of the trench and the gate lines and that extends along the first direction,
wherein a vertical height of the air gap is smaller at a region adjacent the common source and the drains than between the data storing patterns.

### Claim 15 (depends on 14)

The device of claim 14, wherein an uppermost position of the air gap between the data storing patterns is located between a bottom surface of the data storing pattern and a top surface of the data storing pattern, and
wherein the uppermost position of the air gap at a region that is adjacent the common source and the drains is located below a top surface of the semiconductor substrate.

### Claim 16 (depends on 14)

The device of claim 14, further comprising a blocking insulating layer that is between the data storing patterns and the gate line and that extends over the trench,
wherein the air gap exposes a bottom surface of the blocking insulating layer between the data storing patterns that are adjacent one other.

### Claim 17 (depends on 16)

The device of claim 16, wherein the blocking insulating layer conformally covers top and upper side surfaces of the data storing pattern, and
wherein a thickness of the blocking insulating layer is smaller between the data storing patterns than on the top surface of the data storing pattern.

### Claim 18 (depends on 16)

The device of claim 16, wherein the blocking insulating layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially stacked, and
wherein the air gap exposes a portion of the second dielectric layer.

### Claim 19 (depends on 14)

The device of claim 14, further comprising an insulating liner that conformally covers an inner surface of the trench and that is exposed by the air gap.

### Claim 20 (depends on 14)

The device of claim 14, further comprising:
a first selection line that is between the gate line and the common source and that crosses the plurality of first active regions;
a second selection line that is between the gate line and the drains and that crosses the plurality of first active regions; and
an insulating pattern that is spaced apart from the bottom surface of the trench and that is below the first and second selection lines,
wherein the insulating pattern has a top surface positioned over a top surface of the semiconductor substrate and a rounded bottom surface positioned below the top surface of the semiconductor substrate.

### Claim 21 (depends on 14)

The device of claim 14, further comprising:
bit line contact plugs connected to ones of the plurality of drains, respectively; and
a common source line on the second active region and that is electrically connected to the common source, the common source line extending along on the second direction.

### Claim 22 (depends on 14)

The device of claim 14, wherein the data storing pattern comprises a tunnel insulating layer and a floating gate electrode that are sequentially stacked on the semiconductor substrate.

### Claim 23 (depends on 14)

The device of claim 14, wherein the data storing pattern comprises a charge tunneling layer, a charge trap insulating layer, and a charge blocking layer that are sequentially stacked on the semiconductor substrate.

### Claim 24

A semiconductor memory device, comprising:
a semiconductor substrate including active regions defined by a trench;
a gate electrode that crosses the active regions and the trench;
a data storing pattern that is between the gate electrode and the active regions;
a blocking insulating layer that is between the data storing pattern and the gate electrode and that extends over the trench; and
an air gap that is below the blocking insulating layer and that is in the trench,
wherein an uppermost position of the air gap is positioned between a top surface of the data storing pattern and a bottom surface of the data storing pattern, and
wherein the blocking insulating layer is partially exposed by the air gap.

### Claim 25 (depends on 24)

The device of claim 24, wherein the blocking insulating layer conformally covers top and upper side surfaces of the data storing pattern, and
wherein a thickness of the blocking insulating layer is smaller on the trench than on the top surface of the data storing pattern.

### Claim 26 (depends on 24)

The device of claim 24, wherein the blocking insulating layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially stacked, and
wherein the air gap exposes a portion of the second dielectric layer.

### Claim 27 (depends on 24)

The device of claim 24, further comprising an insulating liner that conformally covers an inner surface of the trench and that is exposed by the air gap.

### Claim 28 (depends on 24)

The device of claim 24, further comprising an insulating pattern having a curved surface that is exposed by the air gap and that covers a lower side surface of the data storing pattern below the blocking insulating layer.

### Claim 29 (depends on 24)

The device of claim 24, wherein the data storing pattern comprises a tunnel insulating layer and a floating gate electrode that are sequentially stacked on the semiconductor substrate.

### Claim 30 (depends on 24)

The device of claim 24, wherein the data storing pattern comprises a charge tunneling layer, a charge trap insulating layer, and a charge blocking layer that are sequentially stacked on the semiconductor substrate.

### Claim at position 31

31-47. (canceled)

### Claim 48

A semiconductor memory device, comprising:
a semiconductor substrate including a first trench that defines active regions in a first region and a second trench in a second region around the first region;
a gate electrode on the first region that crosses the active regions;
a data storing pattern that is between the gate electrode and the active regions; and
a blocking insulating layer that is between the gate electrode and the data storing pattern and that extends over the first trench to define an air gap in the first trench.

### Claim 49 (depends on 48)

The device of claim 48, wherein the air gap comprises a first air gap,
the device further comprising an insulating pattern that is spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

### Claim 50 (depends on 49)

The device of claim 49, wherein the first and second trenches have substantially the same depth,
wherein the first air gap includes a first vertical height and the second air gap includes a second vertical height, and
wherein the first vertical height is greater than the second vertical height.

### Claim 51 (depends on 49)

The device of claim 49,
wherein an uppermost position of the first air gap is located between a bottom surface of the data storing pattern and a top surface of the data storing pattern, and
wherein an uppermost position of the second air gap is located below a top surface of the semiconductor substrate.

### Claim 52 (depends on 49)

The device of claim 49, wherein a thickness of the blocking insulating layer is smaller on the first trench than on a top surface of the data storing pattern.

### Claim 53 (depends on 49)

The device of claim 49, wherein the semiconductor substrate has a first conductivity type and comprises:
a well region formed in the semiconductor substrate to have a second conductivity type; and
a pocket well region formed in the well region to have the first conductivity type, and
a well pick-up region locally formed in the pocket well region to have an impurity concentration higher than that of the pocket well region and to have the first conductivity type; and
a well contact plug that is adjacent the second trench in the second region and connected to the semiconductor substrate.

### Claim 54 (depends on 49)

The device of claim 49, wherein the insulating pattern comprises:
a top surface that is positioned on a top surface of the semiconductor substrate; and
a rounded bottom surface that is positioned below the top surface of the semiconductor substrate.

### Claim 55 (depends on 49)

The device of claim 49, wherein the data storing pattern comprises a charge tunneling layer, a charge trap insulating layer, and a charge blocking layer that are sequentially stacked on the semiconductor substrate.

### Claim 56 (depends on 49)

The device of claim 49,
wherein the semiconductor substrate comprises a third trench formed on the second region,
wherein the third trench includes a bottom surface that is lower than a bottom surface of the second trench,
the device further comprising a peripheral insulating pattern spaced apart from the bottom surface of the third trench to define a third air gap in the third trench.

### Claim 57 (depends on 56)

The device of claim 56, wherein an uppermost position of the third air gap is located below an uppermost position of the first air gap, and a lowermost position of the third air gap is located below a lowermost position of the first air gap, and
wherein the third air gap includes a third vertical height that is greater than the second vertical height.