# US 2014/0151776 A1 · Vertical memory cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151776 A1 - Document ID: US20140151776A1 - Status: Published application - Kind: A1 - Application number: 14/090,689 - Filed: 2013-11-26 - Published: 2014-06-05 - Earliest claimed: 2011-07-27 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Kurt D. Beigel; Sanh D. Tang - Web page: https://patentgrep.com/patent/US20140151776A1 ## CPC - H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} - H10B 12/10: DRAM devices comprising bipolar components - H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells} - H10D 30/689: {Vertical floating-gate IGFETs} - H10D 30/711: {having floating bodies} - H10D 62/125: {Shapes of junctions between the regions} - H10D 30/6728: {Vertical TFTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension. ## Claims ### Claim 1 A vertical memory cell, comprising: a semiconductor material located between two electrodes, the semiconductor material having a plurality of doped regions and a junction between each pair of adjacent doped regions; and a gate conductor formed adjacent one of the doped regions, wherein a cross-sectional area of each junction is less than the cross-sectional area of the doped region having a gate conductor formed adjacent thereto. ### Claim 2 (depends on 1) The vertical memory cell of claim 1, wherein a cross-sectional area of a junction involving one side of the doped region having a gate conductor formed adjacent thereto is less than a cross-sectional area of a junction involving an opposite side of the doped region having a gate conductor formed adjacent thereto. ### Claim 3 (depends on 1) The vertical memory cell of claim 1, wherein a cross-sectional area of a junction involving a side of the doped region having a gate conductor formed adjacent thereto nearer a cathode is less than a cross-sectional area of a junction involving an opposite side of the doped region having a gate conductor formed adjacent thereto nearer an anode. ### Claim 4 (depends on 1) The vertical memory cell of claim 1, wherein one dimension of a junction cross-sectional area is reduced relative to a similar dimension of the cross-sectional area of the doped region having a gate conductor formed adjacent thereto. ### Claim 5 (depends on 1) The vertical memory cell of claim 1, wherein two dimensions of a junction cross-sectional area are reduced relative to similar dimensions of the cross-sectional area of the doped region having a gate conductor formed adjacent thereto. ### Claim 6 (depends on 5) The vertical memory cell of claim 5, wherein the cross-sectional area of the first junction is reduced in a second dimension by a reactive ion etch after the at least one gate structure is formed. ### Claim 7 A vertical memory cell, comprising: an N+ doped semiconductor cathode region formed on a cathode conductor; a doped P-type semiconductor P-base region formed on the N+ doped semiconductor cathode region with a first junction therebetween; an N-type semiconductor region formed on the doped P-type semiconductor P-base region with a second junction therebetween; a P+ doped semiconductor anode region formed on the N-type semiconductor region with a third junction therebetween; and at least one gate structure formed adjacent the doped P-type semiconductor P-base region, the at least one gate structure including conductive material offset from the doped P-type semiconductor P-base region by a gate dielectric, wherein a cross-sectional area of at least one of the first, second, or third junctions is less than the cross-sectional area of the doped P-type semiconductor P-base region. ### Claim 8 (depends on 7) The vertical memory cell of claim 7, wherein the cross-sectional area of the first junction is less than the cross-sectional area of the doped P-type semiconductor P-base region. ### Claim 9 (depends on 8) The vertical memory cell of claim 8, wherein the cross-sectional area of the first junction is greater than the cross-sectional area of each of the second and third junctions. ### Claim 10 (depends on 7) The vertical memory cell of claim 7, wherein the cross-sectional area of the second junction is less than the cross-sectional area of the doped P-type semiconductor P-base region. ### Claim 11 (depends on 7) The vertical memory cell of claim 7, wherein the cross-sectional area of the third junction is less than the cross-sectional area of the doped P-type semiconductor P-base region. ### Claim 12 (depends on 11) The vertical memory cell of claim 11, wherein the cross-sectional area of the first junction is reduced in a first dimension by a reactive ion etch before the at least one gate structure is formed. ### Claim 13 (depends on 7) The vertical memory cell of claim 7, wherein the cross-sectional areas of each of the first, second, and third junctions are less than the cross-sectional area of the doped P-type semiconductor P-base region, and the cross-sectional area of each of the second and third junctions are less than the cross-sectional area of the first junction. ### Claim 14 (depends on 7) The vertical memory cell of claim 7, wherein the cross-sectional areas of each of the first, second, and third junctions are reduced in at least a first dimension by oxidizing respective semiconductors near the first, second, and third junctions. ### Claim 15 A vertical memory cell, comprising: a semiconductor structure formed over a conductor line, the semiconductor structure having a first region directly below a body region, the first region including a first junction between first and second doped materials; and an etch-protective material formed on a first pair of sidewalls of the semiconductor structure above the first region; and a gate structure formed adjacent the body region, and wherein a cross-sectional area of the first region is smaller relative to a cross-sectional area of the body region in a first dimension. ### Claim 16 (depends on 15) The vertical memory cell of claim 15, wherein the cross-sectional area of the first region is smaller than the cross-sectional area of the body region in a second dimension, the second dimension being orthogonal to the first dimension. ### Claim 17 (depends on 16) The vertical memory cell of claim 16, wherein the semiconductor structure includes a second junction between second and third doped materials in a second region above the body region, and wherein a cross-sectional area of the second region is smaller than the cross-sectional area of the body region in the first dimension. ### Claim 18 (depends on 17) The vertical memory cell of claim 17, wherein the cross-sectional area of the second region is smaller than the cross-sectional area of the first region in the first dimension. ### Claim 19 (depends on 17) The vertical memory cell of claim 17, wherein a cross-sectional area of the second region is smaller than the cross-sectional area of the body region in the second dimension. ### Claim 20 (depends on 17) The vertical memory cell of claim 17, wherein the third doped material is formed above the second doped material in the second region, and the semiconductor structure includes a fourth doped material formed above the third doped material in the second region, and wherein the first doped material is an N+ doped material, the second doped material is a doped P-base material, the third doped material is an N-base material, and the fourth doped material is a P+ doped material.