# US 2014/0151775 A1 · Control gate

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- Number: US 2014/0151775 A1
- Document ID: US20140151775A1
- Status: Published application
- Kind: A1
- Application number: 14/174,804
- Filed: 2014-02-06
- Published: 2014-06-05
- Earliest claimed: 2009-11-19
- Assignees: GLOBAL FOUNDRIES Singapore Pte. Ltd.
- Applicants: GLOBAL FOUNDRIES Singapore Pte. Ltd.
- Inventors: Shyue Seng TAN; Lee Wee TEO; Chunshan YIN
- Web page: https://patentgrep.com/patent/US20140151775A1

## CPC

- H10D 64/514: {characterised by the insulating layers}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a split gate structure disposed on the substrate, wherein the split gate structure comprises
a second gate disposed on the substrate;
an inter-gate dielectric layer disposed on the substrate and over the second gate;
a first gate, wherein the first gate is adjacent to and separated from the second gate by the inter-gate dielectric layer,
wherein the inter-gate dielectric layer below the first gate and between the first and second gates corresponds to a charge storage layer, the first and second gates include first and second adjacent sidewalls which are adjacent to the first and second gates and first and second non-adjacent sidewalls;
a first diffusion region adjacent to the first non-adjacent sidewall of the first gate and a second diffusion region adjacent to the second non-adjacent sidewall of the second gate; and
an e-field equalizer which at least extends from the first non-adjacent sidewall to below the first gate, wherein the e-field equalizer improves uniformity of an e-field across the first gate during operation to improve charge trapping capabilities of the charge storage layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein the first gate comprises a control gate and the second gate comprises a select gate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1 wherein the first diffusion region comprises a first extension region adjacent to the edge of the first gate and the second diffusion region comprises a second extension region adjacent to the edge of the second gate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1 wherein the first diffusion region serves as a source terminal and the second diffusion region serves as a drain terminal.

### Claim 5 (depends on 1)

The semiconductor device of claim 1 wherein the inter-gate dielectric layer comprises nano-crystals having charge storage capacity.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 wherein the e-field equalizer comprises a heavily doped e-region of a first polarity type adjacent to the first diffusion region and contacts at least a portion of the charge storage layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6 wherein the first and second gates have co-planar top surfaces.

### Claim 8 (depends on 6)

The semiconductor device of claim 6 wherein the e-field equalizer comprises a portion of the inter-gate dielectric layer having a thickness gradient disposed on the substrate and beneath the first gate.

### Claim 9 (depends on 8)

The semiconductor device of claim 8 wherein the thickness gradient is such that it is thicker at an interface of the first and second gates than at the first diffusion region.

### Claim 10 (depends on 6)

The semiconductor device of claim 6 wherein the first gate overlaps the second gate.

### Claim 11 (depends on 1)

The semiconductor device of claim 1 wherein the e-field equalizer comprises a portion of the inter-gate dielectric layer having a thickness gradient disposed on the substrate and beneath the first gate.

### Claim 12 (depends on 11)

The semiconductor device of claim 11 wherein the thickness gradient is such that it is thicker at an interface of the first and second gates than at the first diffusion region.

### Claim 13

A device comprising:
a substrate with a first feature having first and second sidewalls, wherein the first feature includes a dielectric layer which serves as a charge storage layer below the first feature and on the substrate;
a first diffusion region in the substrate adjacent to the first sidewall of the first feature; and
an e-field equalizer which at least extends from the first sidewall to below the first feature, wherein the e-field equalizer improves uniformity of e-field across the distance between the first and second sidewalls of the first feature during operation to improve charge trapping capabilities of the charge storage layer.

### Claim 14 (depends on 13)

The device of claim 13 wherein the e-field equalizer comprises a heavily doped e-region of a first polarity type adjacent to the first diffusion region and contacts at least a portion of the charge storage layer.

### Claim 15 (depends on 14)

The device of claim 14 wherein the e-field equalizer comprises a portion of the dielectric layer having a thickness gradient disposed on the substrate and beneath the first gate.

### Claim 16 (depends on 15)

The device of claim 15 wherein the thickness gradient is such that it is thicker at the second sidewall of the first feature than at the first diffusion region.

### Claim 17 (depends on 13)

The device of claim 13 wherein the e-field equalizer comprises a portion of the dielectric layer having a thickness gradient disposed on the substrate and beneath the first gate.

### Claim 18 (depends on 13)

The device of claim 13 comprises a second feature adjacent to the second sidewall of the first feature.

### Claim 19 (depends on 18)

The device of claim 18 wherein the first and second features have co-planar top surfaces.

### Claim 20 (depends on 18)

The device of claim 18 wherein first feature overlaps the second feature.