# US 2014/0151773 A1 · FINFET eDRAM STRAP CONNECTION STRUCTURE

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- Number: US 2014/0151773 A1
- Document ID: US20140151773A1
- Status: Published application
- Kind: A1
- Application number: 14/064,381
- Filed: 2013-10-28
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Veeraraghavan S. Basker; Effendi Leobandung; Tenko Yamashita; Chun-Chen Yeh
- Web page: https://patentgrep.com/patent/US20140151773A1

## CPC

- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10B 12/0385: {Making a connection between the transistor and the capacitor, e.g. buried strap}
- H10B 12/0387: {Making the trench}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/33: {the capacitor extending under the transistor}
- H10B 12/36: {the transistor being a FinFET}
- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor comprises forming a buried oxide layer in a substrate, the buried oxide layer defining an SOI layer on a surface of the substrate; forming a deep trench through the SOI layer and the buried oxide layer in the substrate; forming a storage capacitor in a lower portion of the deep trench; conformally doping a sidewall of an upper portion of the deep trench; depositing a metal strap on the conformally doped sidewall and on the storage capacitor; forming at least one fin in the SOI layer, the fin being in communication with the metal strap; forming a spacer over the metal strap and over a juncture of the fin and the metal strap; and depositing a passive word line on the spacer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate comprising a buried oxide layer;
a storage capacitor in a lower portion of a deep trench formed in at least the buried oxide layer of the substrate;
a metal strap on a conformally doped surface of an upper portion of a sidewall of the deep trench and on the storage capacitor;
a fin of a transistor disposed on the substrate and in communication with the metal strap;
a spacer formed over a juncture of the fin and the metal strap; and
a PWL deposited over the spacer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising an oxide layer disposed in the upper portion of the sidewall of the deep trench and on the metal strap.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the storage capacitor comprises a high k dielectric material disposed on a sidewall of the lower portion of the deep trench and on the storage capacitor and a conductor disposed on the high k dielectric material.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the high k dielectric material is selected from the group consisting of hafnium dioxide, hafnium silicate, zirconium dioxide, zirconium silicate, and combinations of the foregoing.

### Claim 5 (depends on 3)

The semiconductor structure of claim 3, wherein the conductor is one of a poly conductor and a metal.

### Claim 6

(canceled)

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the conformally doped surface comprises arsine.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the metal strap connects the source areas or drain areas of the fin to the storage capacitor to form a Schottky barrier.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the metal strap comprises a material selected from the group of materials consisting of titanium nitrides, tantalum nitrides, and tantalum aluminum nitrides.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the buried oxide layer comprises SiO2.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein the spacer comprises one or more of SiN, Si3N4, SiO2, and silicon carbon nitride.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein the PWL is a conductive material.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the PWL is tungsten.