# US 2014/0151772 A1 · Uniform finfet gate height

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- Number: US 2014/0151772 A1
- Document ID: US20140151772A1
- Status: Published application
- Kind: A1
- Application number: 13/689,924
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: William Cote; Johnathan E. Faltermeier; Babar A. Khan; Ravikumar Ramachandran; Theodorus E. Standaert; Xinhui Wang
- Web page: https://patentgrep.com/patent/US20140151772A1

## CPC

- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

## Claims

### Claim 1

A method comprising:
providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer;
removing a portion of the plurality of fins to form an opening;
forming a dielectric spacer on a sidewall of the opening;
filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer;
forming a deep trench capacitor in-line with one of the plurality of fins;
removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap; and
removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
removing the oxide layer; and
recessing the fill material such that the top surface of the fill material is substantially flush with a top surface of the fins.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a gate above and between the plurality of fins and the fill material.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the gate comprises using a gate first or a replacement gate process flow.

### Claim 5 (depends on 1)

The method of claim 1, wherein filling the opening with a fill material comprises depositing an oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein providing a plurality of fins etched from a semiconductor substrate comprises providing a bulk substrate or a semiconductor-on-insulator substrate.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the deep trench capacitor further comprises:
forming a deep trench
forming a buried plate;
forming a node dielectric, and
forming an inner electrode.

### Claim 8

A structure comprising:
a first plurality of fins and a second plurality of fins etched from a semiconductor substrate;
a deep trench capacitor positioned in-line with, and electrically connected to, one of the plurality of fins; and
a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, wherein the fill material does not contact either the first plurality of fins or the second plurality of fins.

### Claim 9 (depends on 8)

The structure of claim 8, further comprising:
a gate located above and between the first plurality of fins, the second plurality of fins, and the fill material, wherein the gate comprises at least a different material than the fill material.

### Claim 10 (depends on 8)

The structure of claim 8, wherein the fill material is substantially the same height as the first plurality of fins and the second plurality of fins.

### Claim 11 (depends on 8)

The structure of claim 8, wherein the fill material comprises an oxide.

### Claim 12 (depends on 8)

The structure of claim 8, wherein the semiconductor substrate comprises a bulk substrate or a semiconductor-on-insulator substrate.