# US 2014/0151767 A1 · Method for producing semiconductor device and semiconductor device

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- Number: US 2014/0151767 A1
- Document ID: US20140151767A1
- Status: Published application
- Kind: A1
- Application number: 14/177,459
- Filed: 2014-02-11
- Published: 2014-06-05
- Earliest claimed: 2012-05-18
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Fujio MASUOKA; Hiroki NAKAMURA
- Web page: https://patentgrep.com/patent/US20140151767A1

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6743: {Silicon}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact.

## Claims

### Claim at position 1

-7. (canceled)

### Claim 8

A semiconductor device comprising:
a fin-shaped silicon layer formed on a silicon substrate;
a first insulating film formed around the fin-shaped silicon layer;
a pillar-shaped silicon layer formed on the fin-shaped silicon layer, the width of the pillar-shaped silicon layer being equal to the width of the fin-shaped silicon layer;
a diffusion layer formed in an upper portion of the fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer;
a diffusion layer formed in an upper portion of the pillar-shaped silicon layer;
a silicide formed in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer;
a gate insulating film formed around the pillar-shaped silicon layer;
a metal gate electrode formed around the gate insulating film;
a metal gate line extending in a direction perpendicular to the fin-shaped silicon layer and being connected to the metal gate electrode;
a metal gate pad connected to the metal gate line, the width of the metal gate electrode and the width of the metal gate pad being larger than the width of the metal gate line; and
a contact formed on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer,
wherein the diffusion layer formed in the upper portion of the pillar-shaped silicon layer is directly connected to the contact.