# US 2014/0151765 A1 · Gate-all-around carbon nanotube transistor with selectively doped spacers

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- Number: US 2014/0151765 A1
- Document ID: US20140151765A1
- Status: Published application
- Kind: A1
- Application number: 13/971,150
- Filed: 2013-08-20
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Aaron D. Franklin; Siyuranga O. Koswatta; Joshua T. Smith
- Web page: https://patentgrep.com/patent/US20140151765A1

## CPC

- H10K 10/481: {characterised by the gate conductors}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- B82Y 99/00: Subject matter not provided for in other groups of this subclass
- H10K 85/221: {Carbon nanotubes}
- Y10S 977/842: for carbon nanotubes or fullerenes
- Y10S 977/938: Field effect transistors, FETS, with nanowire- or nanotube-channel region
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method of fabricating a semiconducting device is disclosed. A carbon nanotube is formed on a substrate. A portion of the substrate is removed to form a recess below a section of the carbon nanotube. A doped material is applied in the recess to fabricate the semiconducting device. The recess may be between one or more contacts formed on the substrate separated by a gap.

## Claims

### Claim 1

A semiconducting device, comprising:
a carbon nanotube on a substrate;
a recess formed in a portion of the substrate below a section of the carbon nanotube; and
a doped material in the recess.

### Claim 2 (depends on 1)

The semiconducting device of claim 1, wherein the section of the carbon nanotube is in a gap between a first contact and a second contact formed on the carbon nanotube.

### Claim 3 (depends on 2)

The semiconducting device of claim 2, wherein the first contact and the second contact are aligned to provide a self-aligned gate structure.

### Claim 4 (depends on 1)

The semiconducting device of claim 1, wherein the doped material further comprises a spacer material having a fixed charged density deposited on surfaces of the recess.

### Claim 5 (depends on 4)

The semiconducting device of claim 4, wherein the portion of the substrate in the gap forms a carbon nanotube bridge, further comprising a non-doped high-k dielectric material configured to coat the carbon nanotube bridge.

### Claim 6 (depends on 5)

The semiconducting device of claim 5, wherein the high-k dielectric material is configured to provide a chemical transfer of charge from the doped spacer material to the carbon nanotube bridge.

### Claim 7 (depends on 1)

The semiconducting device of claim 1, wherein the doped material include hafnium oxide.

### Claim 8 (depends on 1)

The semiconducting device of claim 1 wherein the doped material is configured to enable operation of the semiconductor device as an n-type semiconductor.

### Claim 9 (depends on 1)

The semiconducting device of claim 1, wherein the portion of the substrate is configured to be removed via anisotropic etching of the substrate.

### Claim 10

A transistor, comprising:
a carbon nanotube material on a substrate;
one or more contacts formed on the substrate to configured to define a gap between the one or more contacts;
a removed portion of the substrate in the gap; and
a doped material in the removed portion in the gap.

### Claim 11 (depends on 10)

The transistor of claim 10, the carbon nanotube in the in the gap forms a carbon nanotube bridge.

### Claim 12 (depends on 11)

The transistor of claim 11, wherein the doped material further comprises a spacer material having a fixed charged density deposited on exposed surfaces in the gap.

### Claim 13 (depends on 12)

The transistor of claim 12, further comprising a non-doped high-k dielectric material configured to coat the carbon nanotube bridge.

### Claim 14 (depends on 13)

The transistor of claim 13, wherein the high-k dielectric material provides a chemical charge transfer from the doped spacer material to the carbon nanotube bridge.

### Claim 15 (depends on 10)

The transistor of claim 10, wherein the doped material includes hafnium oxide.

### Claim 16 (depends on 10)

The transistor of claim 10, further comprising forming the one or more contacts to provide a self-aligned gate structure of the transistor.

### Claim 17

A self-aligned carbon nanotube transistor, comprising:
a carbon nanotube on a substrate;
a source contact on the substrate over the carbon nanotube;
a drain contact on the substrate over the carbon nanotube, wherein the drain contact is separated from the source contact by a gap;
a recess in the gap between the source contact and the drain contact formed by removing a portion of the substrate in the gap; and
a doped material in the gap.

### Claim 18 (depends on 17)

The self-aligned carbon nanotube transistor of claim 17, wherein the doped material further comprises a spacer material having a dopant deposited on exposed surfaces of the recess except for the carbon nanotube.

### Claim 19 (depends on 18)

The self-aligned carbon nanotube transistor of claim 18, further comprising etching a portion of the spacer material and applying a chemical charge-transfer dopant to the exposed carbon nanotube in the spacer region.

### Claim 20 (depends on 17)

The self-aligned carbon nanotube transistor of claim 17, further comprising a non-doped high-k dielectric material configured to coat the carbon nanotube in the gap.