# US 2014/0151762 A1 · Semiconductor Device and Method of Forming the Same

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- Number: US 2014/0151762 A1
- Document ID: US20140151762A1
- Status: Published application
- Kind: A1
- Application number: 13/693,954
- Filed: 2012-12-04
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, L
- Inventors: Tsan-Chun Wang; Ziwei Fang
- Web page: https://patentgrep.com/patent/US20140151762A1

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/50: Physical imperfections
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 30/0218: {having pocket halo regions selectively formed at the sides of the gates}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10P 30/226: {at a temperature lower than room temperature}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.

## Claims

### Claim 1

A method, comprising:
forming a NMOS gate structure over a substrate;
forming an amorphized region in the substrate adjacent to the NMOS gate structure;
forming a lightly doped source/drain (LDD) region in the amorphized region;
forming a dummy spacer layer over the NMOS gate structure and the substrate after forming the amorphized region;
patterning the dummy spacer layer to form spacers adjoining sidewalls of the NMOS gate structure;
depositing a stress film over the NMOS gate structure;
performing an annealing process; and
removing the stress film.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The method of claim 1, wherein the dummy spacer layer comprises a spacer layer and a liner layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the annealing process forms a dislocation in the substrate adjacent to the NMOS gate structure.

### Claim 5 (depends on 4)

The method of claim 4, wherein the dislocation has a depth less than about 30 nanometers.

### Claim 6 (depends on 4)

The method of claim 4, wherein the dislocation has a proximity less than about 5 nanometers.

### Claim 7 (depends on 1)

The method of claim 1, wherein the amorphized region is formed using an implantation process using a species with atomic mass less than about 28.

### Claim 8 (depends on 1)

The method of claim 1, wherein the amorphized region is formed using an implantation process with a species of silicon (Si).

### Claim 9 (depends on 1)

The method of claim 1, wherein the amorphized region is formed using an implantation process with an implantation dosage of about 1×1014 atoms/cm2 to about 2×1015 atoms/cm2.

### Claim 10 (depends on 1)

The method of claim 1, wherein the amorphized region is formed using an implantation process with an implant energy less than about 20 KeV.

### Claim 11 (depends on 1)

The method of claim 1, wherein there is not a sidewall spacer adjoining a sidewall of the NMOS gate structure when forming the amorphized region.

### Claim 12 (depends on 1)

The method of claim 1, wherein the stress film provides tensile stress in the annealing process.

### Claim 13

A method of manufacturing a semiconductor device, comprising:
forming a NMOS gate structure and a PMOS gate structure over a substrate;
forming a protector over the PMOS gate structure;
performing an implantation process using a silicon species to form amorphized regions in the substrate adjacent to opposite edges of the NMOS gate structure;
forming lightly doped source/drain (LDD) regions in the amorphized regions;
forming spacers adjoining sidewalls of the NMOS gate structure and the PMOS gate structure;
depositing a stress film over the spacers, the NMOS gate structure, and the PMOS gate structure;
performing an annealing process to recrystallize the amorphized regions; and
removing the stress film.

### Claim 14 (depends on 13)

The method of claim 13, wherein the implantation process is performed using an implant energy less than about 20 KeV.

### Claim 15

(canceled)

### Claim 16 (depends on 13)

The method of claim 13, wherein the annealing process forms a dislocation with a proximity less than about 3 nanometers in the substrate adjacent to the NMOS gate structure.

### Claim 17 (depends on 13)

The method of claim 13, wherein the amorphized regions have a thickness less than about 150 nanometers.

### Claim 18

A semiconductor device, comprising:
a NMOS gate structure over a substrate; and
a dislocation in the substrate adjacent to an edge of the NMOS gate structure, wherein the dislocation has a proximity less than about 3 nanometers and the dislocation has a depth less than about 30 nanometers.

### Claim 19 (depends on 18)

The device of claim 18, wherein the NMOS gate structure includes source/drain (S/D) regions having a species of Si but without germanium (Ge) therein.

### Claim 20 (depends on 18)

The device of claim 18, wherein the dislocation has a proximity less than about 1 nanometer.