# US 2014/0151759 A1 · Facet-free strained silicon transistor

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- Number: US 2014/0151759 A1
- Document ID: US20140151759A1
- Status: Published application
- Kind: A1
- Application number: 13/692,632
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: STMicroelectronics S.r.l.
- Applicants: Stmicroelectronics, Inc.
- Inventors: Nicolas Loubet; Prasanna Khare; Qing Liu
- Web page: https://patentgrep.com/patent/US20140151759A1

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

## Claims

### Claim at position 1

1-6. (canceled)

### Claim 7

A structure for use in an integrated circuit, the structure comprising:
an embedded region of oxide having a conformal nitride layer thereover; and
a substantially facet-free epitaxially grown region of a silicon compound adjacent to the embedded region of oxide.

### Claim 8 (depends on 7)

The structure of claim 7 wherein the embedded region of oxide is an isolation trench and the conformal nitride covering is a silicon nitride trench liner.

### Claim 9 (depends on 7)

The structure of claim 7 wherein a thickness of the conformal nitride covering is in the range of about 3 nm-12 nm.

### Claim 10 (depends on 7)

The structure of claim 7 wherein the epitaxial silicon compound is silicon germanium.

### Claim 11 (depends on 7)

The structure of claim 7 wherein the epitaxial silicon compound is silicon carbide.

### Claim 12

A transistor comprising:
a pair of isolation trenches extending below a surface of a silicon substrate, the trenches lined with silicon nitride liners that define nitride-silicon boundaries within the substrate;
a gate structure formed on the surface of the silicon substrate between the trenches, the gate structure including:
a gate dielectric;
a bulk gate layer;
a pair of spacers; and
epitaxial source and drain regions extending between the gate structure and the trenches, the source and drain regions being substantially facet-free near the nitride-silicon boundaries.

### Claim 13 (depends on 12)

The transistor of claim 12 wherein a thickness of the silicon nitride liners is in the range of about 3 nm-12 nm.

### Claim 14

A silicon transistor, comprising
a means of modifying electric charge mobility in a silicon substrate by replacing regions of bulk silicon with regions of an epitaxially-grown silicon compound;
a means of substantially suppressing faceting during epitaxial growth of the silicon compound adjacent to an embedded oxide structure; and
a means for controlling current flow between the epitaxially grown regions.

### Claim 15 (depends on 14)

The silicon transistor of claim 14 wherein the means for controlling current flow between the epitaxially grown regions includes a gate separated from the silicon substrate by a gate dielectric.

### Claim 16 (depends on 14)

The silicon transistor of claim 14 wherein the means of substantially suppressing faceting adjacent to an embedded oxide structure includes providing a nitride covering around the embedded oxide structure.

### Claim at position 12

17-20. (canceled)