# US 2014/0151758 A1 · Semiconductor Device and Method of Manufacturing a Semiconductor Device

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- Number: US 2014/0151758 A1
- Document ID: US20140151758A1
- Status: Published application
- Kind: A1
- Application number: 13/692,397
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Andreas Meiser; Till Schloesser
- Web page: https://patentgrep.com/patent/US20140151758A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0287: {using recessing of the source electrodes}
- H10D 30/0289: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/658: {having trench gate electrodes}
- H10D 62/051: {Forming charge compensation regions, e.g. superjunctions}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/111: {Field plates}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a ridge extending along the first direction and the drift zone including a superjunction layer stack.

## Claims

### Claim 1

A semiconductor device comprising a transistor formed in a semiconductor substrate having a first main surface, the transistor comprising:
a source region;
a drain region;
a channel region;
a drift zone; and
a gate electrode at the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region,
the channel region and the drift zone disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the channel region having a shape of a ridge extending along the first direction, and
the drift zone comprising a superjunction layer stack.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode is disposed at least two sides of the ridge.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the ridge comprises a top side and two sidewalls, the sidewalls extending along the first direction.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein a conductive inversion layer is formed along at least one of the sidewalls when the device is operated in an on-state.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising a field plate that is disposed adjacent to the superjunction layer stack.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the ridge of the channel region fulfills the following relationship: d1≦2×ld, wherein ld denotes a length of a depletion zone formed at an interface between the channel region and a gate dielectric, the gate dielectric being disposed between the channel region and the gate electrode.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the superjunction layer stack comprises n-doped and p-doped layers being stacked in a stack direction in an alternating manner, the stack direction being perpendicular with respect to the first main surface.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the superjunction layer stack comprises n-doped layers and p-doped layers being arranged in a stack direction in an alternating manner, the stack direction extending in a direction parallel to the first main surface and perpendicular with respect to a depth direction.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the length s1 of the ridge measured along the first direction and a width d1 of the ridge measured perpendicularly with respect to the first direction fulfills the following relationship s1/d1>2.0.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the source and the drain region are disposed within the semiconductor substrate and extend approximately to a depth to which the gate electrode extends from the first main surface in a depth direction of the semiconductor substrate.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein at least one of the source region and the drain region extends to a depth which is more than 1 μm.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the superjunction layer stack comprises at least two n-doped or at least two p-doped layers.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a source contact, coupled to the source region; and
a drain contact, coupled to the drain region,
wherein the source contact extends to the first main surface and the drain contact extends to a second main surface that is opposite to the first main surface, and wherein the drain region is insulated at a region of the first main surface.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a source contact, coupled to the source region; and
a drain contact, coupled to the drain region,
wherein the drain contact extends to the first main surface and the source contact extends to a second main surface that is opposite to the first main surface, and wherein the source region is insulated at a region of the first main surface.

### Claim 15

A method of manufacturing a semiconductor device comprising forming a transistor in a semiconductor substrate having a first main surface, wherein forming the transistor comprises:
forming a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to the channel region, wherein the channel region and the drift zone are formed to be disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, wherein forming the channel region comprises forming a ridge extending along the first direction, and forming the drift zone comprises forming a superjunction layer stack.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the superjunction layer stack comprises epitaxially growing a sequence of differently doped layers.

### Claim 17 (depends on 16)

The method of claim 16, wherein growing the sequence of differently doped layers is accomplished by sequentially interchanging the source of dopants fed during a growth process of growing the differently doped layers.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming the channel region is performed after forming the superjunction layer stack, and wherein forming the channel region comprises an epitaxial growth process.

### Claim 19 (depends on 15)

The method of claim 15, wherein forming the ridge and forming the gate electrode is accomplished by a method comprising forming gate trenches in the channel region and forming a conductive layer so as to fill adjacent trenches, the gate trenches extending in the first direction.

### Claim 20

A semiconductor device comprising a transistor formed in a semiconductor substrate having a first main surface, the transistor comprising:
a source region;
a drain region;
a channel region;
a drift zone; and
a gate electrode at the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region, the gate electrode being insulated from the channel region by a gate dielectric,
the channel region and the drift zone disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the drift zone comprising a superjunction layer stack, the superjunction layer stack comprising n-doped and p-doped layers stacked in a stack direction in an alternating manner, the stack direction being perpendicular with respect to the first main surface, and
at least one of the source region and the drain region extending to a depth so that a bottom boundary between the source region or the drain region and the semiconductor substrate is disposed beneath a bottom interface between the n-doped and p-doped layers of the layer stack.