# US 2014/0151757 A1 · Substrate-templated epitaxial source/drain contact structures

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- Number: US 2014/0151757 A1
- Document ID: US20140151757A1
- Status: Published application
- Kind: A1
- Application number: 13/692,162
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Anirban Basu; Josephine B. Chang; Michael A. Guillorn; Amlan Majumdar
- Web page: https://patentgrep.com/patent/US20140151757A1

## CPC

- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/435: {having multiple laterally adjacent 1D material channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/01: {Manufacture or treatment}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Single crystalline semiconductor fins are formed on a single crystalline buried insulator layer. After formation of a gate electrode straddling the single crystalline semiconductor fins, selective epitaxy can be performed with a semiconductor material that grows on the single crystalline buried insulator layer to form a contiguous semiconductor material portion. The thickness of the deposited semiconductor material in the contiguous semiconductor material portion can be selected such that sidewalls of the deposited semiconductor material portions do not merge, but are conductively connected to one another via horizontal portions of the deposited semiconductor material that grow directly on a horizontal surface of the single crystalline buried insulator layer. Simultaneous reduction in the contact resistance and parasitic capacitance for a fin field effect transistor can be provided through the contiguous semiconductor material portion and cylindrical contact via structures.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming at least one semiconductor material portion on a single crystalline dielectric layer;
forming a gate electrode straddling said at least one semiconductor material portion; and
forming a contiguous single crystalline semiconductor portion directly on an end subportion of each of said at least one semiconductor material portion by depositing a semiconductor material in epitaxial alignment with said single crystalline dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein said at least one semiconductor material portion has a doping of a first conductivity type, and said method further comprises doping said end subportion of each of said at least one semiconductor material portion with dopants of a second conductivity type that is the opposite of said first conductivity type.

### Claim 3 (depends on 1)

The method of claim 1, further comprising recessing a portion of a top surface of said single crystalline dielectric layer, wherein said contiguous single crystalline semiconductor portion is formed directly on said recessed portion of said top surface of said single crystalline dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein said at least one semiconductor material portion is a plurality of semiconductor fins having parallel vertical sidewalls.

### Claim 5 (depends on 4)

The method of claim 4, wherein each of said plurality of semiconductor fins is single crystalline and is in epitaxial alignment with said single crystalline dielectric layer.

### Claim 6 (depends on 5)

The method of claim 5, further comprising forming a shallow trench isolation structure on said single crystalline dielectric layer, wherein vertical surfaces of said at least one semiconductor material portion contact said shallow trench isolation structure.

### Claim 7 (depends on 6)

The method of claim 6, wherein each of said at least one semiconductor material portion extends along a horizontal lengthwise direction, has a substantially rectangular vertical cross-sectional shape within vertical planes perpendicular to said horizontal lengthwise direction.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
forming a gate spacer laterally around said gate electrode; and
removing physically exposed portions of said at least one semiconductor portion that are not covered by said gate electrode or said gate spacer, wherein end surfaces of said at least one semiconductor portion are vertically coincident with outer sidewalls of said gate spacer after said removal of said physically exposed portions.

### Claim 9 (depends on 1)

The method of claim 1, wherein said at least one semiconductor material portion is a plurality of semiconductor nanowires.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a first semiconductor pad and a second semiconductor pad over said single crystalline dielectric layer, wherein each first end of said semiconductor nanowire is attached to said first semiconductor pad, and each second end of said semiconductor nanowire is attached to said second semiconductor pad.

### Claim 11 (depends on 9)

The method of claim 9, further comprising
forming a plurality semiconductor fins laterally contacting said first and second semiconductor pads;
removing portions of said single crystalline dielectric layer from underneath said plurality of semiconductor fins; and
converting said plurality of semiconductor fins into a plurality of semiconductor nanowires by an anneal.

### Claim 12 (depends on 9)

The method of claim 9, wherein said gate electrode wraps around each of said plurality of semiconductor nanowires.

### Claim 13 (depends on 9)

The method of claim 9, wherein said plurality of semiconductor nanowires extends along a horizontal lengthwise direction, and has a uniform vertical cross-sectional shape along said horizontal lengthwise direction.

### Claim 14

A semiconductor structure comprising:
a substrate including a single crystalline dielectric layer;
at least one semiconductor material portion located on said single crystalline dielectric layer;
a gate electrode straddling said at least one semiconductor material portion; and
a contiguous single crystalline semiconductor portion contacting an end subportion of each of said at least one semiconductor material portion and having a single crystalline structure in epitaxial alignment with said single crystalline dielectric layer.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein a subportion of each of said at least one semiconductor material portion underlying said gate electrode has a doping of a first conductivity type, and said end subportion of each of said at least one semiconductor material portion has a doping of a second conductivity type that is the opposite of said first conductivity type.

### Claim 16 (depends on 14)

The semiconductor structure of claim 14, wherein each of said at least one semiconductor material portion is single crystalline, and is in epitaxial alignment with said single crystalline dielectric layer.

### Claim 17 (depends on 14)

The semiconductor structure of claim 14, wherein said at least one semiconductor material portion is a plurality of semiconductor material portions.

### Claim 18 (depends on 14)

The semiconductor structure of claim 14, wherein a top surface of a bottom subportion of said contiguous single crystalline semiconductor portion is located below a topmost surface of said at least one semiconductor material portion.

### Claim 19 (depends on 14)

The semiconductor structure of claim 14, further comprising a shallow trench isolation structure located above said single crystalline dielectric layer and laterally surrounding said at least one semiconductor material portion.

### Claim 20 (depends on 14)

The semiconductor structure of claim 14, wherein said at least one semiconductor material portion is a plurality of semiconductor fins having parallel vertical sidewalls.

### Claim 21 (depends on 20)

The semiconductor structure of claim 20, wherein each of said plurality of semiconductor fins is single crystalline and is in epitaxial alignment with said single crystalline dielectric layer.

### Claim 22 (depends on 14)

The semiconductor structure of claim 14, wherein said at least one semiconductor material portion is a plurality of semiconductor nanowires.

### Claim 23 (depends on 22)

The semiconductor structure of claim 22, wherein each first end of said semiconductor nanowire is attached to a first semiconductor pad, and each second end of said semiconductor nanowire is attached to a second semiconductor pad.

### Claim 24 (depends on 23)

The semiconductor structure of claim 23, wherein a bottommost surface of said plurality of semiconductor nanowires is located above a topmost surface of said single crystalline dielectric layer.

### Claim 25 (depends on 23)

The semiconductor structure of claim 23, wherein said plurality of semiconductor nanowires extends along a horizontal lengthwise direction, and has a uniform vertical cross-sectional shape along said horizontal lengthwise direction.