# US 2014/0151756 A1 · Fin field effect transistors including complimentarily stressed channels

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- Number: US 2014/0151756 A1
- Document ID: US20140151756A1
- Status: Published application
- Kind: A1
- Application number: 13/692,144
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Josephine B. Chang; Paul Chang; Michael A. Guillorn; Amlan Majumdar
- Web page: https://patentgrep.com/patent/US20140151756A1

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A stressed single crystalline epitaxial semiconductor layer having a first type stress is formed on a single crystalline substrate layer. First and second semiconductor fins are formed by patterning the stressed single crystalline epitaxial semiconductor layer. A center portion of each first semiconductor fin is undercut to form a recessed region, while the bottom surface of each second semiconductor fin maintains epitaxial registry with the single crystalline substrate layer. The center portion of each first semiconductor fin is under a second type of stress, which is the opposite of the first type of stress. A first field effect transistor formed on the first semiconductor fins can include first channels under the second type of stress along direction of current flow, and a second field effect transistor formed on the second semiconductor fins can include second channels under the first type of stress along the direction of current flow.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming at least one semiconductor fin on a single crystalline substrate layer, said at least one semiconductor fin comprising a single crystalline semiconductor material epitaxially aligned to, and lattice-mismatched from, said single crystalline substrate layer and extending along a lengthwise direction; and
forming a recessed region in said single crystalline substrate layer, wherein a first end portion and a second end portion of each of said at least one semiconductor fin remains in contact with a top surface of said single crystalline substrate layer and a center portion of each of said at least one semiconductor fin overlies said recessed region.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a field effect transistor by:
forming a source region in each first end portion of said at least one semiconductor fin; and
forming a drain region in each second end portion of said at least one semiconductor fin.

### Claim 3 (depends on 2)

The method of claim 2, wherein said center portion of each of said at least one semiconductor fin includes a body region of said field effect transistor.

### Claim 4 (depends on 2)

The method of claim 2, wherein said first and second end portions of each of said at least one semiconductor fin are under a first type of stress, and center portion is under a second type of stress that is the opposite of said first type of stress.

### Claim 5 (depends on 4)

The method of claim 4, wherein said first type of stress is a compressive stress and said second type of stress is a tensile stress.

### Claim 6 (depends on 4)

The method of claim 4, wherein said first type of stress is a tensile stress and said second type of stress is a compressive stress.

### Claim 7 (depends on 2)

The method of claim 2, further comprising forming a gate dielectric directly on at least a portion of said recessed surface of said recessed region, and directly on sidewall surfaces, a top surface, and a bottom surface of each of said at least one semiconductor fin.

### Claim 8 (depends on 7)

The method of claim 7, wherein said gate dielectric includes a hole through which a center portion of one said at least one semiconductor fin passes.

### Claim 9 (depends on 7)

The method of claim 7, further comprising forming a gate electrode on said gate dielectric, wherein said gate electrode is formed between a recessed surface of said recessed region and a bottom surface of each of said at least one semiconductor fin, and over and around each of said at least one semiconductor fin.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a gate spacer around said gate electrode and directly on portions of said recessed surface of said recessed region.

### Claim 11 (depends on 10)

The method of claim 10, wherein said gate spacer is formed directly on sidewalls of said gate electrode.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
forming a disposable gate structure over each center portion of said at least one semiconductor fin;
forming a gate spacer around said disposable gate structure; and
removing said disposable gate structure to form a gate cavity, wherein said gate electrode is formed in said gate cavity.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming a gate electrode, wherein said recessed region is formed in said single crystalline substrate layer prior to forming said gate electrode.

### Claim 14

A semiconductor structure comprising:
a single crystalline substrate layer including a recessed region that is recessed relative to a top surface of said single crystalline substrate layer; and
a semiconductor fin comprising a single crystalline semiconductor material including first and second end portions that are in contact with said top surface of said single crystalline substrate layer and epitaxially aligned to said single crystalline substrate layer and including a center portion that overlies said recessed region, wherein said single crystalline semiconductor material is lattice-mismatched with respect to said single crystalline substrate layer.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein said semiconductor comprises a field effect transistor that includes:
a body region including said center portion and having a doping of a first conductivity type;
a source region including said first end portion and having a doping of a second conductivity type that is the opposite of said first conductivity type; and
a drain region including said second end portion and having a doping of said second conductivity type.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein said first and second end portions are under a first type of stress along a lengthwise direction of said semiconductor fin, and said center portion is under a second type of stress that is the opposite of said first type of stress.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein said first type of stress is a compressive stress and said second type of stress is a tensile stress.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein said first type of stress is a tensile stress and said second type of stress is a compressive stress.

### Claim 19 (depends on 15)

The semiconductor structure of claim 15, wherein said field effect transistor further comprises a gate electrode that includes a portion located between a recessed surface of said recessed region and a bottom surface of said semiconductor fin.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein an entirety of said gate electrode is a single contiguous structure that includes at least one hole therein, wherein said center portion of said semiconductor fin passes through one of said at least one hole.

### Claim 21 (depends on 19)

The semiconductor structure of claim 19, further comprising a gate dielectric that contacts at least a portion of said recessed surface of said recessed region, sidewall surfaces of said center portion, a top surface of said center portion, and a bottom surface of said center portion.

### Claim 22 (depends on 19)

The semiconductor structure of claim 19, wherein said field effect transistor further comprises a gate spacer that laterally surrounds said gate electrode and contacts portions of said recessed surface of said recessed region.

### Claim 23 (depends on 19)

The semiconductor structure of claim 19, wherein an entirety of said semiconductor fin has a same vertical cross-sectional shape within vertical planes that are perpendicular to a lengthwise direction of said semiconductor fin.

### Claim 24 (depends on 19)

The semiconductor structure of claim 19, further comprising a gate spacer having a bottommost surface that is located at or above a topmost surface of said semiconductor fin.

### Claim 25 (depends on 15)

The semiconductor structure of claim 15, wherein said field effect transistor further comprises:
a raised source region that is epitaxially aligned to said source region; and
a raised drain region that is epitaxially aligned to said drain region.