# US 2014/0151744 A1 · Power semiconductor devices

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- Number: US 2014/0151744 A1
- Document ID: US20140151744A1
- Status: Published application
- Kind: A1
- Application number: 14/093,126
- Filed: 2013-11-29
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Baik-woo LEE; Seong-woon BOOH
- Web page: https://patentgrep.com/patent/US20140151744A1

## CPC

- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 90/00: Package configurations
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W 72/01936: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/07531: {Techniques}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/07536: {Soldering or alloying}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.

## Claims

### Claim 1

A power semiconductor device, comprising:
a lower structure;
a solder layer on the lower structure;
a semiconductor structure on the solder layer;
a contact layer on the semiconductor structure;
a pad layer on the contact layer; and
a wire between the pad layer and the lower structure;
wherein the solder layer is electrically connected to a first electrode of the semiconductor structure.

### Claim 2 (depends on 1)

The power semiconductor device of claim 1, wherein the lower structure comprises a copper pattern layer electrically connected to the first electrode via the solder layer.

### Claim 3 (depends on 1)

The power semiconductor device of claim 1, wherein the lower structure comprises:
a copper pattern layer;
a copper layer; and
a ceramic layer between the copper pattern layer and the copper layer.

### Claim 4 (depends on 1)

The power semiconductor device of claim 1, wherein the semiconductor structure comprises:
the first electrode and a second electrode on a first surface of the semiconductor structure; and
a third electrode on a second surface of the semiconductor structure.

### Claim 5 (depends on 4)

The power semiconductor device of claim 4, wherein the semiconductor structure is an insulated gate bipolar transistor (IGBT) structure,
wherein the first electrode is a gate,
wherein the second electrode is an emitter,
wherein the third electrode is a collector, and
wherein the gate and the emitter are electrically connected to the solder layer.

### Claim 6 (depends on 5)

The power semiconductor device of claim 5, wherein the collector is electrically connected to the pad layer.

### Claim 7 (depends on 4)

The power semiconductor device of claim 4, wherein the semiconductor structure is a metal-oxide semiconductor field-effect transistor (MOSFET) structure,
wherein the first electrode is a gate,
wherein the second electrode is a source,
wherein the third electrode is a drain, and
wherein the gate and the source are electrically connected to the solder layer.

### Claim 8 (depends on 7)

The power semiconductor device of claim 7, wherein the drain is electrically connected to the pad layer.

### Claim 9 (depends on 1)

The power semiconductor device of claim 1, further comprising:
a trench in a boundary region between the pad layer and the contact layer.

### Claim 10 (depends on 1)

The power semiconductor device of claim 1, wherein the solder layer comprises a first solder layer and a second solder layer on the lower structure,
wherein the semiconductor structure is on the first solder layer,
wherein a diode structure is on the second solder layer,
wherein the contact layer and the pad layer are on each of the semiconductor structure and the diode structure, and
wherein each of the pad layers is electrically connected to the lower structure via the wire.

### Claim 11 (depends on 10)

The power semiconductor device of claim 10, wherein the semiconductor structure comprises an insulated gate bipolar transistor (IGBT) or a metal-oxide semiconductor field-effect transistor (MOSFET).

### Claim 12 (depends on 10)

The power semiconductor device of claim 10, wherein the diode structure comprises:
an anode;
a diode material layer; and
a cathode.

### Claim 13 (depends on 12)

The power semiconductor device of claim 12, wherein the diode structure is electrically connected to the lower structure via the second solder layer.

### Claim 14 (depends on 10)

The power semiconductor device of claim 10, further comprising:
a trench in a boundary region between the pad layer and the contact layer.

### Claim 15 (depends on 1)

The power semiconductor device of claim 1, wherein the contact layer is formed of a same material as the solder layer.